UCC21220AD from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	INA	input	Input signal for the A channel with a TTL/CMOS compatible threshold, pulled low internally if left open and recommended to be tied to ground if unused.
2	INB	input	Input signal for the B channel with a TTL/CMOS compatible threshold, pulled low internally if left open and recommended to be tied to ground if unused.
3	VCCI	power_in	Primary-side supply voltage that must be locally decoupled to GND with a low ESR/ESL capacitor placed as close to the device as possible.
4	GND	power_in	Primary-side ground reference to which all primary-side signals are referenced.
5	DIS	input	Disables both driver outputs when asserted high or left open (pulled high internally) and enables them when set low, with tying to ground recommended if unused.
6	NC	unconnected	No internal connection.
7	NC	unconnected	No internal connection.
8	VCCI	power_in	Primary-side supply voltage that is internally shorted to pin 3 and should be decoupled to GND with a low ESR/ESL capacitor close to the device.
9	VSSB	power_in	Ground reference for the secondary-side B channel driver.
10	OUTB	output	Output of driver B, connected to the gate of the B channel FET or IGBT.
11	VDDB	power_in	Secondary-side power supply for driver B, locally decoupled to VSSB with a low ESR/ESL capacitor placed as close to the device as possible.
12	NC	unconnected	No internal connection.
13	NC	unconnected	No internal connection.
14	VSSA	power_in	Ground reference for the secondary-side A channel driver.
15	OUTA	output	Output of driver A, connected to the gate of the A channel FET or IGBT.
16	VDDA	power_in	Secondary-side power supply for driver A, locally decoupled to VSSA with a low ESR/ESL capacitor placed as close to the device as possible.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-16
Category	Power Management (PMIC)
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input bias pin supply voltage VCCI to GND		-0.3		6	V	VCCI to GND	4
Driver bias supply VDDA-VSSA, VDDB-VSSB		-0.3		30	V	VDDA-VSSA, VDDB-VSSB	4
Output signal voltage OUTA to VSSA, OUTB to VSSB		-0.3			V	max VVDDA+0.3, VVDDB+0.3	4
Output signal voltage transient OUTA to VSSA, OUTB to VSSB		-2			V	Transient for 200 ns; max VVDDA+0.3, VVDDB+0.3	4
Input signal voltage INA, INB, DIS to GND		-0.3			V	max VVCCI+0.3	4
Junction temperature TJ	TJ	-40		150	°C		4
Storage temperature	Tstg	-65		150	°C		4
VCCI Input supply voltage	VCCI	3		5.5	V		4
Driver output bias supply VDDA, VDDB (UCC21220A, 5V UVLO)	VDDA, VDDB	6.5		25	V	UCC21220A - 5V UVLO Version	4
Junction Temperature	TJ	-40		150	°C		4
VCCI quiescent current	IVCCI		1.4	2	mA	VINA = 0 V, VINB = 0 V	8
VDDA and VDDB quiescent current	IVDDA, IVDDB		1.2	2	mA	VINA = 0 V, VINB = 0 V	8
VCCI operating current	IVCCI		2.7	3.2	mA	f = 500 kHz, current per channel	8
VDDA and VDDB operating current	IVDDA, IVDDB		2.7	4.4	mA	f = 500 kHz, current per channel, VVDDA, VVDDB = 12 V	8
UVLO Rising threshold (VCCI)	VVCCI_ON	2.55	2.7	2.85	V		8
UVLO Falling threshold (VCCI)	VVCCI_OFF	2.35	2.5	2.65	V		8
UVLO Rising threshold (VDD, 5-V UVLO version)	VVDDA_ON, VVDDB_ON	5.7	6	6.3	V	UCC21220A 5-V UVLO version	8
UVLO Falling threshold (VDD, 5-V UVLO version)	VVDDA_OFF, VVDDB_OFF	5.4	5.7	6	V	UCC21220A 5-V UVLO version	8
UVLO Threshold hysteresis (VDD, 5-V UVLO version)	VVDDA_HYS, VVDDB_HYS		0.3		V	UCC21220A 5-V UVLO version	8
Input high threshold voltage	VINAH, VINBH, VDISH		2	2.3	V		8
Input low threshold voltage	VINAL, VINBL, VDISL	0.8	1		V		8
Input threshold hysteresis	VINA_HYS, VINB_HYS, VDIS_HYS		1		V		8
Peak output source current	IOA+, IOB+		-4		A	CVDD = 10 µF, CLOAD = 0.22 µF, f = 1 kHz, bench measurement	8
Peak output sink current	IOA-, IOB-		6		A	CVDD = 10 µF, CLOAD = 0.22 µF, f = 1 kHz, bench measurement	8
Output resistance at high state	ROHA, ROHB		5		Ω	IOUT = -5 mA	8
Output resistance at low state	ROLA, ROLB		0.55		Ω	IOUT = 5 mA	8
Driver output active pull down	VOAPDA, VOAPDB		1.6	2	V	VVDDA and VVDDB unpowered, IOUTA, IOUTB = 200 mA	8
Minimum input pulse width that passes to output	tPWmin	4	12	30	ns	Output does not change the state if input signal less than tPWmin	9
Propagation delay at falling edge	tPDHL	26	33	45	ns	INx high threshold, VINH, to 10% of the output	9
Propagation delay at rising edge	tPDLH	26	33	45	ns	INx low threshold, VINL, to 90% of the output	9
Pulse width distortion in each channel	tPWD			5	ns	/tPDLHA, tPDHLA/, /tPDLHB, tPDHLB/	9
Propagation delay matching	tDM			6.5	ns	Input Pulse Width = 100ns, 500kHz, TJ = -40°C to -10°C	9
Propagation delay matching	tDM			5	ns	Input Pulse Width = 100ns, 500kHz, TJ = -10°C to +150°C	9
VCCI Power-up Delay Time: UVLO rise to OUTA, OUTB	tVCCI+ to OUT	18	42	80	µs	INA or INB tied to VCCI	9
VDDA, VDDB Power-up Delay Time: UVLO rise to OUTA, OUTB	tVDD+ to OUT			10	µs	INA or INB tied to VCCI	9
High-level common-mode transient immunity	/CMH/	125			V/ns	Slew rate of GND vs. VSSA/B, INA and INB both tied to GND or VCCI; VCM=1000 V	9
Low-level common-mode transient immunity	/CML/	125			V/ns	Slew rate of GND vs. VSSA/B, INA and INB both tied to GND or VCCI; VCM=1000 V	9
Output rise time	tRISE		8		ns	CVDD = 10 µF, COUT = 1.8 nF, VVDDA, VVDDB = 12 V, f = 1 kHz	9
Output fall time	tFALL		8		ns	CVDD = 10 µF, COUT = 1.8 nF, VVDDA, VVDDB = 12 V, f = 1 kHz	9
Junction-to-ambient thermal resistance	RθJA		80.2		°C/W	D (SOIC) 16 pins	5
Junction-to-case (top) thermal resistance	RθJC(top)		36.6		°C/W	D (SOIC) 16 pins	5
Junction-to-board thermal resistance	RθJB		45		°C/W	D (SOIC) 16 pins	5
Junction-to-top characterization parameter	ψJT		28		°C/W	D (SOIC) 16 pins	5
Junction-to-board characterization parameter	ψJB		44.3		°C/W	D (SOIC) 16 pins	5
Power dissipation	PD		950		mW	VCCI = 5 V, VDDA/B = 20 V, INA/B = 3.3 V, 460kHz 50% duty cycle, 2.2-nF load, TJ=150℃, TA=25℃	5
Power dissipation by transmitter side	PDI		50		mW		5
Power dissipation by each driver side	PDA, PDB		450		mW		5

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		• Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended, with priority	33

CAD (KiCad official)

Symbol: UCC21220AD
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: ucc21220ad-etched.step / ucc21220ad-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc21220ad.step / ucc21220ad.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (45 pp, sha256 71440c65170dc667, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

UCC21220AD

Verified UCC21220AD

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