component
UC3845BDTR
Public Made by Adomby adom
XBLW UC3845BDTR XBLW AC-DC Controllers and Regulators, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
main
Ray
uc3845bdtr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
defff71
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"title": "UC3845BDTR",
"brief": "XBLW UC3845BDTR XBLW AC-DC Controllers and Regulators, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
"version": "0.2.0",
"license": "CC-BY-SA-4.0",
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"mpn": "UC3845BDTR",
"manufacturer": "XBLW UC3845BDTR XBLW",
"package": "SOP-8",
"pin_count": 8,
"category": "PMIC",
"subcategory": "AC-DC Controllers and Regulators",
"datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2310191806_XBLW-UC3845BDTR-XBLW_C18723588.pdf",
"parts": {
"symbol": "uc3845bdtr.kicad_sym",
"footprint": "uc3845bdtr.kicad_mod",
"model_3d": "uc3845bdtr-etched.glb",
"model_3d_plain": "uc3845bdtr.glb",
"model_3d_step": "uc3845bdtr-etched.step",
"model_3d_step_plain": "uc3845bdtr.step",
"lbr": "uc3845bdtr.lbr"
},
"distributor_links": {},
"pins": [
{
"number": "1",
"name": "COMP",
"type": "output",
"description": "Error amplifier compensation output. Connect external compensation network (Zf) between this pin and VFB (pin 2) to shape the error-amplifier loop response."
},
{
"number": "2",
"name": "VFB",
"type": "input",
"description": "Inverting input of the internal error amplifier used to close the voltage-feedback loop of the power converter. Typically compared against the internal 2.5 V reference at the non-inverting input."
},
{
"number": "3",
"name": "ISENSE",
"type": "input",
"description": "Primary-side current-sense input. Connect to the current-sensing resistor; the PWM uses this signal (max threshold ~1.0 V, gain 3 V/V) to terminate OUTPUT switch conduction on a cycle-by-cycle basis."
},
{
"number": "4",
"name": "RT/CT",
"type": "passive",
"description": "Oscillator timing node. Connect timing resistor RT from this pin to VREF and timing capacitor CT from this pin to GROUND to set the switching frequency (up to 500 kHz) and maximum output duty cycle."
},
{
"number": "5",
"name": "GND",
"type": "power_in",
"description": "Device ground return. Timing and bypass capacitors must be tied to this pin at a single point to avoid ground-current disturbance of the analog sections."
},
{
"number": "6",
"name": "OUTPUT",
"type": "output",
"description": "High-current totem-pole gate driver output for an external power MOSFET. Peak source/sink currents up to 1 A; enters high-impedance state during UVLO."
},
{
"number": "7",
"name": "VCC",
"type": "power_in",
"description": "Positive supply input to the device. Operating range up to 30 V absolute maximum; UVLO turn-on 8.2 V typ, turn-off 7.6 V typ (UC3845B). Internal zener clamp ~34 V."
},
{
"number": "8",
"name": "VREF",
"type": "power_out",
"description": "Buffered 5.0 V (±2%) internal reference output. Provides charging current to the oscillator timing capacitor through the timing resistor and can source up to ~20 mA for external circuitry."
}
],
"provenance": {
"extractor": "ds2sf",
"datasheet": {
"url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2310191806_XBLW-UC3845BDTR-XBLW_C18723588.pdf",
"pages": 14,
"sha256": "2785bb3bf513f1c6",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 8,
"described": 8,
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}
},
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"pin1": {
"pad": "1",
"at": [
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-1.905
],
"corner": "top-left",
"source": "silk-marker",
"derived_from": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4",
"mark": "drawn"
},
"models_3d": [
{
"file": "uc3845bdtr.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6,
4.9,
1.75
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "uc3845bdtr-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6,
4.9,
1.75
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "a767e270a5c5639f3cb7f865eeb68dabe0b3b8317f290c526c0df2d917dbffcf",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "XBLW",
"Package": "SOP-8",
"Category": "PMIC",
"Pins": "8"
}
},
"sections": [
"hero",
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"info"
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"discovery_triggers": [
"uc3845bdtr"
],
"discovery_pitch": "UC3845BDTR (XBLW UC3845BDTR XBLW) component page with datasheet-verified CAD.",
"author": {
"name": "Ray"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"uc3845bdtr.kicad_sym",
"uc3845bdtr.kicad_mod",
"uc3845bdtr.glb",
"uc3845bdtr.step",
"uc3845bdtr-etched.step",
"uc3845bdtr.lbr",
"docs/hero.png",
"docs/uc3845bdtr-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html"
],
"visibility": {
"public": true
},
"variants": [
{
"mpn": "UC3845BDTR",
"kind": "packaging"
},
{
"mpn": "UC3845BDTRAN",
"kind": "packaging"
}
],
"updated_at": "2026-09-25T13:32:55.473Z"
}