component
UC3844ADTR
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownUC3844ADTR
Texas Instruments · AC-DC Controllers And Regulators · SOIC-14
UC3844ADTR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Low-impedance 1MHz error amplifier output (80dB open-loop gain) serving as peak-current-limit or PWM comparator input; maximum sink current 6mA, internally not current-limited. |
| 2 | NC | unconnected | No connection. |
| 3 | FB | input | Error amplifier input for power converter voltage feedback control to achieve loop stability. |
| 4 | NC | unconnected | No connection. |
| 5 | ISENSE | input | Peak-current-limit or PWM comparator input; when used with current-sense resistor, error amplifier output controls per-cycle peak current limit with maximum signal internally clamped to 1V. |
| 6 | NC | unconnected | No connection. |
| 7 | RT/CT | input | Oscillator input programmed with external timing resistor (5kΩ to 100kΩ recommended) and capacitor (470pF to 4.7nF recommended). |
| 8 | PGND | power_in | Power and gate-driver return path; enables star-ground technique to redirect gate-driver current away from signal ground, reducing PWM controller instability. |
| 9 | GND | power_in | Controller signal ground. |
| 10 | OUTPUT | output | 1A totem-pole gate-driver output capable of sourcing and sinking up to 1A gate current; gate-drive resistor required for current limiting. |
| 11 | VC | power_in | Gate-driver bias input requiring bias capacitor at least 10x the main switch FET gate capacitance; provides gate-driver biasing in devices without separate VCC pin. |
| 12 | VCC | power_in | Gate-driver bias input (11V minimum recommended); requires bypass capacitor at least 10x larger than VREF pin capacitor. |
| 13 | NC | unconnected | No connection. |
| 14 | VREF | power_out | 5V regulated reference output; maximum load current 10mA during normal operation, short-circuit protected at approximately 100mA; requires 1µF high-frequency bypass capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Power Management (PMIC) |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
UC3844ADTR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
uc3844adtr-etched.step/uc3844adtr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);uc3844adtr.step/uc3844adtr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (54 pp, sha256
7b502cab841be227, retrieved 2026-09-27, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).