component
UC3842N
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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UC3842N
Texas Instruments · AC-DC Controllers And Regulators · PDIP-8
UC3842N from Texas Instruments, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier compensation pin for the external compensation network; the error amplifier is internally current-limited, and COMP can be forced to GROUND externally to set zero duty cycle. |
| 2 | VFB | input | Inverting input of the internal error amplifier used for the voltage feedback loop, with the non-inverting input trimmed to 2.5 V; keep the VFB lead short and its stray capacitance minimal for stability. |
| 3 | ISENSE | input | Primary-side current-sense input to the PWM comparator, connected to the MOSFET current-sense resistor, which terminates the OUTPUT on-time; the recommended VISENSE input voltage is 1 V maximum. |
| 4 | RT/CT | bidirectional | Oscillator timing pin: timing resistor RT connects from VREF and timing capacitor CT connects to GROUND to set the switching frequency via fOSC = 1.72/(RRT×CCT), and RRT must never be less than 5 kΩ. |
| 5 | GROUND | power_in | Combined signal and power ground return; with no separate PWRGND pin on this 8-pin package, GROUND serves as both analog and power ground, and the datasheet recommends separating the signal return from the high-current gate-driver path. |
| 6 | OUTPUT | output | Totem-pole gate driver for the external MOSFET, sourcing and sinking peak current up to 1 A, and held actively low when VCC is below the turn-on threshold. |
| 7 | VCC | power_in | Analog controller bias supply input, recommended at 12 V to 28 V with a 30 V absolute maximum from a low-impedance source, requiring a 0.1 µF bypass capacitor to GROUND placed close to the pin. |
| 8 | VREF | power_out | 5 V reference output used by the error amplifier, internal circuits and the oscillator timing network; it requires a ceramic bypass capacitor of at least 0.1 µF to GROUND placed close to the pin, and any external load needs additional bypass. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
UC3842N - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: PDIP-8 (KiCad packages3D, STEP)
- 3D model files:
uc3842n-etched.step/uc3842n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);uc3842n.step/uc3842n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (61 pp, sha256
0f875fd24cbb5fda, retrieved 2026-10-10, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).