component

UC3842BDTR

Public Made by Adom

by adom

XBLW UC3842BDTR XBLW AC-DC Controllers and Regulators, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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PCB Footprint

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Datasheet

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Contents

README

markdown

UC3842BDTR

XBLW · AC-DC Controllers and Regulators · SOP-8

UC3842BDTR from XBLW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 COMP output Error amplifier compensation pin. Connect external compensation components to this pin to modify the error amplifier output for loop stability.
2 VFB input Voltage Feedback. Inverting input to the internal error amplifier. VFB is used to control the power converter voltage-feedback loop for stability. Internal reference is 2.5 V (typ).
3 ISENSE input Primary-side current sense input. Connect to current sensing resistor. The PWM uses this signal to terminate the OUTPUT switch conduction. Max threshold ~1 V.
4 RT/CT passive Oscillator timing pin. Connect timing resistor RT to VREF and timing capacitor CT to GROUND from this pin to set the switching frequency and maximum output ratio. Maximum frequency up to 500 kHz.
5 GND power_in Ground reference for control circuitry and power return.
6 OUTPUT output Gate drive for the external power MOSFET. Peak currents of up to 1 A are sourced and sunk by this pin. Output rise/fall time ~50 ns typical into 1 nF.
7 VCC power_in Power supply input to the device. UVLO startup threshold ~16 V, min operating ~10 V; absolute max 30 V. Internal 29 V zener clamp.
8 VREF power_out 5 V (typ) reference output. Used to provide charging current to the oscillator timing capacitor through the timing resistor. Short-circuit current typ -100 mA.

Key specifications

Parameter Value
Manufacturer XBLW
Package SOP-8
Category PMIC
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • UC3842BDTR
  • UC3842BDTRAN

CAD (KiCad official)

  • Symbol: UC3842BDTR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: uc3842bdtr-etched.step / uc3842bdtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); uc3842bdtr.step / uc3842bdtr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
uc3842bdtr.step 122 KB You want the bare part, or you mark your own boards.
uc3842bdtr-etched.step 2.4 MB You want the part with UC3842BDTR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 580 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XBLW datasheet (12 pp, sha256 35c0919c953ebbf6, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF