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Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	uc3842bd: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
viewers	uc3842bd: viewers · Ray	1mo ago
package.json	uc3842bd: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray	1mo ago
page.json	uc3842bd: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray	1mo ago
README.md	Initial commit: component/uc3842bd · Ray	1mo ago
uc3842bd-etched.fit.json	uc3842bd: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
uc3842bd-etched.glb	uc3842bd: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
uc3842bd-etched.step	uc3842bd: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
uc3842bd.glb	Publish 0.1.0 · Ray	1mo ago
uc3842bd.kicad_mod	Publish 0.1.0 · Ray	1mo ago
uc3842bd.kicad_sym	Publish 0.1.0 · Ray	1mo ago
uc3842bd.lbr	Publish 0.1.0 · Ray	1mo ago
uc3842bd.step	Publish 0.1.0 · Ray	1mo ago

UC3842BD

COSINE · AC-DC Controllers And Regulators · SOP-8

UC3842BD from COSINE, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	COMP	output	Output of error amplifier for compensation; connect external compensation components to this pin or externally force to GROUND to command zero duty cycle.
2	VFB	input	Inverting input to error amplifier, normally connected to switching power supply output through resistor divider.
3	ISENSE	input	Input for voltage proportional to inductor current to terminate output switch conduction; voltage ramp can be applied for voltage-mode control configuration.
4	RT/CT	bidirectional	Program oscillator frequency and maximum output duty cycle by connecting resistor RT to VREF and capacitor CT to ground; operation up to 1 MHz is possible.
5	GROUND	power_in	Ground return pin functioning as both power ground and analog ground.
6	OUTPUT	output	Output of on-chip drive stage directly driving power MOSFET gate with peak current up to 1 A sourced and sunk; output is actively held low when VCC is below turnon threshold.
7	VCC	power_in	Power supply pin for control IC (7.6 V to 30 V); bypass with 0.1 µF ceramic low ESL capacitor with minimal trace lengths and additional bypass capacitor at least 10 times greater than gate capacitance of main switching MOSFET.
8	VREF	power_in	5 V reference providing charging current for capacitor CT through resistor RT; bypass with 0.1 µF ceramic low ESL capacitor with minimal trace length to ground plane.

Key specifications

Parameter	Value
Manufacturer	COSINE
Package	SOP-8
Category	Power Management (PMIC)
Pins	8

CAD (KiCad official)

Symbol: UC3842BD
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOP-8 (KiCad packages3D, STEP)
3D model files: uc3842bd-etched.step / uc3842bd-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); uc3842bd.step / uc3842bd.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: COSINE datasheet (10 pp, sha256 60a0f42408f6f9e3, retrieved 2026-09-21, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF