component
UC3842ADTR
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownUC3842ADTR
Texas Instruments · AC-DC Controllers And Regulators · SOIC-14
UC3842ADTR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Low-impedance 1MHz error amplifier output and peak current limit/PWM comparator input with 80dB open-loop gain; maximum sink current 6mA. |
| 2 | NC | unconnected | No connection. |
| 3 | FB | input | Error amplifier input for power converter voltage feedback loop stability control. |
| 4 | NC | unconnected | No connection. |
| 5 | ISENSE | input | Peak current limit/PWM comparator input; peak current sense signal clamped to 1V; controls cycle-by-cycle peak current limit with external current sense resistor. |
| 6 | NC | unconnected | No connection. |
| 7 | RT/CT | input | Internal oscillator input; programmed with external resistor RT (5kΩ-100kΩ) and capacitor CT (470pF-4.7nF). |
| 8 | PGND | power_in | Power ground and gate driver return path; enables star grounding technique to reduce gate driver-induced PWM instability. |
| 9 | GND | power_in | Controller signal ground. |
| 10 | OUTPUT | output | 1A totem-pole gate driver output; sink/source capability up to 1A; external gate resistor required to limit gate drive current. |
| 11 | VC | power_in | Gate driver bias voltage input; requires bypass capacitor at least 10 times gate capacitance of main switch FET. |
| 12 | VCC | power_in | Gate driver power supply input; requires bypass capacitor with capacitance at least 10 times larger than main switch FET gate capacitance. |
| 13 | NC | unconnected | No connection. |
| 14 | VREF | power_in | 5V reference voltage output; maximum output current 10mA; short-circuit protected at ~100mA; requires 1µF high-frequency bypass capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Power Management (PMIC) |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
UC3842ADTR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
uc3842adtr-etched.step/uc3842adtr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);uc3842adtr.step/uc3842adtr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (54 pp, sha256
1f5ad8805f414728, retrieved 2026-10-06, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).