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UC2846N

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Texas Instruments AC-DC Controllers And Regulators, PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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UC2846N

Texas Instruments · AC-DC Controllers And Regulators · PDIP-16

UC2846N from Texas Instruments, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 C/S SS input Current limit/soft-start programming pin, with a maximum soft-start sink current of 50 mA per the absolute maximum ratings.
2 VREF power_in 5.1-V reference voltage output that requires an external capacitor of 1 µF to 2.2 µF (2.2 µF nominal) and has a maximum reference output current of -30 mA.
3 C/S- input Current sense comparator inverting input; analog inputs are limited to -0.3 V to +VIN and the maximum differential current-sense signal is 1.2 V.
4 C/S+ input Current sense comparator non-inverting input; analog inputs are limited to -0.3 V to +VIN and the maximum differential current-sense signal is 1.2 V.
5 E/A+ input Error amplifier non-inverting input (the pin table misprints this as inverting), with a common-mode range of 0 V to VIN - 2 V.
6 E/A- input Error amplifier inverting input, with analog inputs limited to -0.3 V to +VIN and a common-mode range of 0 V to VIN - 2 V.
7 COMP bidirectional Error amplifier output and input to the PWM comparator, with an absolute maximum output current of -5 mA.
8 CT input Oscillator frequency programming capacitor pin; CT together with RT sets the oscillator frequency and output deadtime.
9 RT input Oscillator frequency programming resistor pin (labelled CR in the pin table); oscillator charging current is rated at a maximum of 5 mA.
10 Sync bidirectional Synchronization I/O for a master controller output or slave controller input; sync output current is limited to -5 mA and the sync output swings between 2.3-2.5 V low and 3.9-4.35 V high.
11 A Out output PWM drive signal output A, complementary to output B (pin 14); output current source or sink is rated at 500 mA maximum.
12 GND power_in Ground reference node to which all signals are referenced.
13 VC power_in Bias supply input for the output stage, with a collector supply voltage limit of 40 V and to be connected through a resistance directly to VIN.
14 B Out output PWM drive signal output B, complementary to output A (pin 11); output current source or sink is rated at 500 mA maximum.
15 VIN power_in Bias supply input with a supply voltage limit of 40 V, decoupled with low-ESR ceramic capacitance placed as close as possible to GND.
16 Shutdown input External shutdown signal input; a signal greater than 350 mV latches the outputs off, with analog inputs limited to -0.3 V to +VIN.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-16
Category Power Management (PMIC)
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (Pin 15) 40 V 4
Collector Supply Voltage (Pin 13) 40 V 4
Output Current, Source or Sink (Pins 11, 14) 500 mA 4
Analog Inputs (Pins 3, 4, 5, 6, 16) -0.3 V Upper limit printed as +VIN 4
Reference Output Current (Pin 2) -30 mA 4
Sync Output Current (Pin 10) -5 mA 4
Error Amplifier Output Current (Pin 7) -5 mA 4
Soft Start Sink Current (Pin 1) 50 mA 4
Oscillator Charging Current (Pin 9) 5 mA 4
Power Dissipation at TA = 25°C 1000 mW TA = 25°C 4
Power Dissipation at TC = 25°C 2000 mW TC = 25°C 4
Storage Temperature Tstg -65 150 °C 4
VREF Terminal External Capacitance 1 2.2 µF 4
Output Voltage (Reference) 5.05 5.1 5.15 V TJ = 25°C, IO = 1 mA 5
Line Regulation 5 20 mV VIN = 8 V to 40 V 5
Load Regulation 3 15 mV IL = 1 mA to 10 mA 5
Line, Load, and Total Output Variation (Reference) 5 5.2 V Over temperature range (1) 5
Short Circuit Output Current (Reference) -10 -45 mA VREF = 0 V 5
Voltage Stability (Oscillator) -1 2 % VIN = 8 V to 40 V 5
Initial Accuracy (Oscillator) 39 43 47 kHz TJ = 25°C 5
Sync Output High Level 3.9 4.35 V 5
Sync Output Low Level 2.3 2.5 V 5
Sync Input High Level 3.9 V Pin 8 = 0 V 5
Sync Input Low Level 2.5 V Pin 8 = 0 V 5
Sync Input Current 1.3 1.5 mA Sync voltage = 3.9 V, Pin 8 = 0 V 5
Input Offset Voltage (Error Amplifier) 0.5 5 mV 5
Input Bias Current (Error Amplifier) -0.6 -1 µA 5
Input Offset Current (Error Amplifier) 40 250 nA 5
Common Mode Range (Error Amplifier) 0 V VIN = 8 V to 40 V 5
Open Loop Voltage Gain (Error Amplifier) 80 105 dB ΔVO = 1.2 to 3 V, VCM = 2 V 5
Unity Gain Bandwidth (Error Amplifier) 0.7 1 MHz TJ = 25°C 5
CMRR (Error Amplifier) 75 100 dB VCM = 0 V to 38 V, VIN = 40 V 5
PSRR (Error Amplifier) 80 105 dB VIN = 8 V to 40 V 5
Output Sink Current (Error Amplifier) 2 6 mA VID = -15 mV to -5 V, VPIN7 = 1.2 V 5
Output Source Current (Error Amplifier) -0.4 -0.5 mA VID = 15 mV to -5 V, VPIN7 = 2.5 V 5
High Level Output Voltage (Error Amplifier) 4.3 4.6 V RL = 15 kΩ (Pin 7) 5
Low Level Output Voltage (Error Amplifier) 0.7 1 V RL = 15 kΩ (Pin 7) 5
Amplifier Gain (Current Sense Amplifier) 2.5 2.75 3 V VPIN3 = 0 V, Pin 1 open 5
Maximum Differential Input Signal (VPIN 4 - VPIN 3) 1.1 1.2 V Pin 1 open; RL = 15 kΩ (Pin 7) 6
Input Offset Voltage (Current Sense Amplifier) 5 25 mV VPIN1 = 0.5 V, Pin 7 open 6
Input Bias Current (Current Sense Amplifier) -2.5 -10 µA VPIN1 = 0.5 V, Pin 7 open 6
Input Common Mode Range (Current Sense Amplifier) 0 V 6
Delay to Outputs (Current Sense) 200 500 ns TJ = 25°C 6
Current Limit Offset 0.45 0.5 0.55 V VPIN3 = 0 V, VPIN4 = 0 V, Pin 7 open 6
Current Limit Input Bias Current -10 -30 µA VPIN5 = VREF, VPIN6 = 0 V 6
Shutdown Threshold Voltage 250 350 400 mV 6
Minimum Latching Current (IPIN1) 3 mA Current into Pin 1 ensured to latch circuit in shutdown state 6
Maximum Latching Current (IPIN1) 1.5 mA Current into Pin 1 ensured not to latch circuit in shutdown state 6
Delay to Outputs (Shutdown) 300 600 ns TJ = 25°C 6
Collector-Emitter Voltage 40 V 6
Collector Leakage Current 200 µA VC = 40 V 6
Output Low Level 0.1 0.4 V ISINK = 20 mA 6
Output Low Level 0.4 2.1 V ISINK = 100 mA 6
Output High Level 13 13.5 V ISOURCE = 20 mA 6
Output High Level 12 13.5 V ISOURCE = 100 mA 6
Rise Time 50 300 ns CL = 1 nF, TJ = 25°C 6
Fall Time 50 300 ns CL = 1 nF, TJ = 25°C 6
Start-Up Threshold (UVLO) 7.7 8 V 6
Supply Current 17 21 mA 6
Thermal Resistance Junction-to-Ambient (N, PDIP) RθJA 41.8 °C/W N or DW package column; N = PDIP 4

CAD (KiCad official)

  • Symbol: UC2846N
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: PDIP-16 (KiCad packages3D, STEP)
  • 3D model files: uc2846n-etched.step / uc2846n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); uc2846n.step / uc2846n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (24 pp, sha256 0d1e2750f80a16be, retrieved 2026-10-15, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF