component
UC2843N
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Texas Instruments AC-DC Controllers And Regulators, DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+45@@ -0,0 +1,45 @@+# UC2843N++**Texas Instruments** · AC-DC Controllers And Regulators · DIP-8++UC2843N from Texas Instruments, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | COMP | output | Error amplifier compensation pin: external compensation network connects here to shape the open-collector error amplifier output, and forcing COMP to GROUND gives zero duty cycle. |+| 2 | VFB | input | Inverting input of the internal error amplifier used for the voltage feedback loop, with the non-inverting input trimmed to 2.5 V; keep the VFB trace as short as possible and stray capacitance as low as possible for stability. |+| 3 | ISENSE | input | Primary-side current-sense input to the PWM comparator that terminates OUTPUT conduction, with a typical 1 V maximum input signal (VISENSE 0.9 V to 1.1 V), and an RC filter may be needed to prevent false triggering from leading-edge noise. |+| 4 | RT/CT | bidirectional | Oscillator timing pin: a timing resistor RT from VREF and timing capacitor CT to GROUND set fOSC = 1.72/(RT×CT), where RT must never be less than 5 kΩ and the recommended CT range is 1 nF to 100 nF. |+| 5 | GROUND | power_in | Combined signal and power ground for this 8-pin package (no separate PWRGND); keep the timing capacitor and bypass returns short and direct to this pin and separate the signal return from the high-current gate-drive path. |+| 6 | OUTPUT | output | Totem-pole gate driver for an external MOSFET that sources and sinks peak current up to 1 A (absolute maximum output drive current ±1 A) and is actively held low while VCC is below the turn-on threshold. |+| 7 | VCC | power_in | Controller supply input with a recommended range of 12 V to 28 V and a 30 V absolute maximum from a low-impedance source (internal clamp typically 34 V); bypass directly to GROUND with a 0.1 µF capacitor placed close to the pin. |+| 8 | VREF | power_in | 5 V reference output (±2% tolerance) that powers the oscillator and internal logic; bypass with at least a 0.1 µF ceramic capacitor placed close to the pin, and recommended reference output current is -20 mA maximum. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | DIP-8 |+| Category | Power Management (PMIC) |+| Pins | 8 |++## CAD (KiCad official)++- Symbol: `UC2843N`+- Footprint: `Package_DIP:DIP-8_W7.62mm`+- 3D model: DIP-8 (KiCad packages3D, STEP)+- 3D model files: `uc2843n-etched.step` / `uc2843n-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `uc2843n.step` / `uc2843n.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/uc3842) (61 pp, sha256 `0f875fd24cbb5fda`, retrieved 2026-10-07, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/uc2843n-datasheet.pdf)
page.jsonadded+200@@ -0,0 +1,200 @@+{+ "slug": "uc2843n",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments AC-DC Controllers And Regulators, DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "uc2843n",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "uc2843n.kicad_sym",+ "uc2843n.kicad_mod",+ "uc2843n.glb",+ "uc2843n.step",+ "uc2843n.lbr",+ "docs/hero.png",+ "docs/uc2843n-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "uc2843n-hero.glb",+ "uc2843n-hero.overlay.json"+ ],+ "component": {+ "mpn": "UC2843N",+ "manufacturer": "Texas Instruments",+ "package": "DIP-8",+ "pin_count": 8,+ "category": "Power Management (PMIC)",+ "subcategory": "AC-DC Controllers And Regulators",+ "datasheet": "https://www.ti.com/cn/lit/gpn/uc3842",+ "parts": {+ "symbol": "uc2843n.kicad_sym",+ "footprint": "uc2843n.kicad_mod",+ "model_3d": "uc2843n-hero.glb",+ "model_3d_plain": "uc2843n.glb",+ "model_3d_step": "uc2843n-etched.step",+ "model_3d_step_plain": "uc2843n.step",+ "lbr": "uc2843n.lbr"+ },+ "distributor_links": {+ "lcsc": "C701458",+ "digikey": "296-11181-5-ND",+ "mouser": "595-UC2843N"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T21:43:58Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-11181-5-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-UC2843N",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "COMP",+ "type": "output",+ "description": "Error amplifier compensation pin: external compensation network connects here to shape the open-collector error amplifier output, and forcing COMP to GROUND gives zero duty cycle."+ },+ {+ "number": "2",+ "name": "VFB",+ "type": "input",+ "description": "Inverting input of the internal error amplifier used for the voltage feedback loop, with the non-inverting input trimmed to 2.5 V; keep the VFB trace as short as possible and stray capacitance as low as possible for stability."+ },+ {+ "number": "3",+ "name": "ISENSE",+ "type": "input",+ "description": "Primary-side current-sense input to the PWM comparator that terminates OUTPUT conduction, with a typical 1 V maximum input signal (VISENSE 0.9 V to 1.1 V), and an RC filter may be needed to prevent false triggering from leading-edge noise."+ },+ {+ "number": "4",+ "name": "RT/CT",+ "type": "bidirectional",+ "description": "Oscillator timing pin: a timing resistor RT from VREF and timing capacitor CT to GROUND set fOSC = 1.72/(RT×CT), where RT must never be less than 5 kΩ and the recommended CT range is 1 nF to 100 nF."+ },+ {+ "number": "5",+ "name": "GROUND",+ "type": "power_in",+ "description": "Combined signal and power ground for this 8-pin package (no separate PWRGND); keep the timing capacitor and bypass returns short and direct to this pin and separate the signal return from the high-current gate-drive path."+ },+ {+ "number": "6",+ "name": "OUTPUT",+ "type": "output",+ "description": "Totem-pole gate driver for an external MOSFET that sources and sinks peak current up to 1 A (absolute maximum output drive current ±1 A) and is actively held low while VCC is below the turn-on threshold."+ },+ {+ "number": "7",+ "name": "VCC",+ "type": "power_in",+ "description": "Controller supply input with a recommended range of 12 V to 28 V and a 30 V absolute maximum from a low-impedance source (internal clamp typically 34 V); bypass directly to GROUND with a 0.1 µF capacitor placed close to the pin."+ },+ {+ "number": "8",+ "name": "VREF",+ "type": "power_in",+ "description": "5 V reference output (±2% tolerance) that powers the oscillator and internal logic; bypass with at least a 0.1 µF ceramic capacitor placed close to the pin, and recommended reference output current is -20 mA maximum."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet table lists VCC as type 'I' (input); it is mapped to power_in because it is the contro; The datasheet table lists RT/CT as type 'I/O'; it is mapped to bidirectional. The datasheet also giv; COMP is listed as type 'O' in the datasheet, but the error amplifier output is open-collector and ca"+ ],+ "pages_sent": 38,+ "cost_usd": 0.2241,+ "at": "2026-10-07T21:43:42"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/uc3842",+ "pages": 61,+ "sha256": "0f875fd24cbb5fda",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 8,+ "described": 8,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "uc2843n.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "body on z = 0, through-hole leads below",+ "extents_mm": [+ 7.874,+ 9.27,+ 6.98+ ],+ "zmin_mm": -3.3,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "4a377a56a8d9e9c0b86c095ef9ecc1869ac19e7f5069a3247b294250bf4f235d",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "uc2843n-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "body on z = 0, through-hole leads below",+ "extents_mm": [+ 7.874,+ 9.27,+ 6.98+ ],+ "zmin_mm": -3.3,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "cbc8f3257401baa238fd87355c87a2a261d660661182ce02b646e10d636aebca",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}