component
UC2843N
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownUC2843N
Texas Instruments · AC-DC Controllers And Regulators · DIP-8
UC2843N from Texas Instruments, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier compensation pin: external compensation network connects here to shape the open-collector error amplifier output, and forcing COMP to GROUND gives zero duty cycle. |
| 2 | VFB | input | Inverting input of the internal error amplifier used for the voltage feedback loop, with the non-inverting input trimmed to 2.5 V; keep the VFB trace as short as possible and stray capacitance as low as possible for stability. |
| 3 | ISENSE | input | Primary-side current-sense input to the PWM comparator that terminates OUTPUT conduction, with a typical 1 V maximum input signal (VISENSE 0.9 V to 1.1 V), and an RC filter may be needed to prevent false triggering from leading-edge noise. |
| 4 | RT/CT | bidirectional | Oscillator timing pin: a timing resistor RT from VREF and timing capacitor CT to GROUND set fOSC = 1.72/(RT×CT), where RT must never be less than 5 kΩ and the recommended CT range is 1 nF to 100 nF. |
| 5 | GROUND | power_in | Combined signal and power ground for this 8-pin package (no separate PWRGND); keep the timing capacitor and bypass returns short and direct to this pin and separate the signal return from the high-current gate-drive path. |
| 6 | OUTPUT | output | Totem-pole gate driver for an external MOSFET that sources and sinks peak current up to 1 A (absolute maximum output drive current ±1 A) and is actively held low while VCC is below the turn-on threshold. |
| 7 | VCC | power_in | Controller supply input with a recommended range of 12 V to 28 V and a 30 V absolute maximum from a low-impedance source (internal clamp typically 34 V); bypass directly to GROUND with a 0.1 µF capacitor placed close to the pin. |
| 8 | VREF | power_in | 5 V reference output (±2% tolerance) that powers the oscillator and internal logic; bypass with at least a 0.1 µF ceramic capacitor placed close to the pin, and recommended reference output current is -20 mA maximum. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | DIP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
UC2843N - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files:
uc2843n-etched.step/uc2843n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);uc2843n.step/uc2843n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (61 pp, sha256
0f875fd24cbb5fda, retrieved 2026-10-07, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).