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docs uc2843d8tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
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page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 10d ago
README.md uc2843d8tr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 13d ago
uc2843d8tr-etched.fit.json uc2843d8tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
uc2843d8tr-etched.glb uc2843d8tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
uc2843d8tr-etched.step uc2843d8tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
uc2843d8tr.glb Publish 0.1.0 · Ray 1mo ago
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uc2843d8tr.step Publish 0.1.0 · Ray 1mo ago

UC2843D8TR

Texas Instruments · DC-DC Converters · SOIC-8

UC2843D8TR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 COMP output Error amplifier compensation pin. Connect external compensation components to modify the error amplifier output. The error amplifier is internally current-limited; forcing COMP to GROUND commands zero duty cycle.
2 VFB input Inverting input to the internal error amplifier. VFB is used to control the power converter voltage-feedback loop for stability. Internal reference is 2.5 V.
3 ISENSE input Primary-side current sense input. Connect to the current sensing resistor; the PWM uses this signal to terminate OUTPUT switch conduction. Max input 1 V; a voltage ramp can be applied here for voltage-mode control.
4 RT/CT bidirectional Fixed-frequency oscillator set point. Connect a timing resistor R_RT to VREF and timing capacitor C_CT to GROUND to set the switching frequency. f_OSC = 1.72 / (R_RT * C_CT); R_RT must be >=5 kΩ. Up to 500 kHz operation.
5 GROUND power_in Analog and power ground return for the device. In the 8-pin package (no separate PWRGND), GROUND serves as both analog and power ground.
6 OUTPUT output Gate drive for the external N-channel MOSFET. On-chip totem-pole driver sources and sinks peak currents up to 1 A. OUTPUT is actively held low when VCC is below the turnon (UVLO) threshold.
7 VCC power_in Analog controller bias input that also powers the gate driver in the 8-pin package. Recommended supply 12-28 V; abs max 30 V (self-limiting above I_VCC = 30 mA). Requires a ~0.1 µF bypass to GROUND plus an additional bypass at least 10x the gate capacitance of the switching FET.
8 VREF power_out 5 V trimmed reference output. Provides charging current to the oscillator timing capacitor through R_RT. Requires a minimum 0.1 µF ceramic bypass to GROUND close to the pin. Max load current 20 mA.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category PMIC
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • UC2843D8TRD
  • UC2843D8TR
  • UC2843D8TRDR
  • UC2843D8TRN
  • UC2843D8TRP
  • UC2843D8TRJ
  • UC2843D8TRJG
  • UC2843D8TRD14
  • UC2843D8TRDW
  • UC2843D8TRW
  • UC2843D8TRFK

CAD (KiCad official)

  • Symbol: UC2843D8TR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: uc2843d8tr-etched.step / uc2843d8tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); uc2843d8tr.step / uc2843d8tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (56 pp, sha256 0a519514b4917848, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF