UC2843D

Texas Instruments · AC-DC Controllers And Regulators · SOIC-14

UC2843D from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	COMP	output	Error amplifier compensation pin: external compensation connects here to shape the error amplifier output, and forcing COMP to GROUND externally sets zero duty cycle; the amplifier has internal current limiting and can source and sink current.
2	NC	unconnected	Not connected (不连接) in the 14-pin SOIC package.
3	VFB	input	Inverting input of the internal error amplifier used to close the voltage feedback loop; keep the lead short and stray capacitance low for stability, and the non-inverting reference input is trimmed to 2.5 V.
4	NC	unconnected	Not connected (不连接) in the 14-pin SOIC package.
5	ISENSE	input	Primary-side current-sense input to the PWM comparator, connected to the current-sense resistor, which terminates OUTPUT conduction; the sense signal is typically 1 V at maximum and a ramp may be applied for voltage-mode or slope compensation.
6	NC	unconnected	Not connected (不连接) in the 14-pin SOIC package.
7	RT/CT	bidirectional	Oscillator timing pin: a timing resistor RT from VREF and timing capacitor CT to GROUND set fOSC = 1.72/(RT×CT); RT must never be below 5 kΩ and CT is recommended between 1 nF and 100 nF.
8	PWRGND	power_in	Power ground for the high-current output driver stage, kept separate from the analog GROUND so switching currents do not disturb the control circuitry.
9	GROUND	power_in	Signal and analog ground return for the controller; the timing capacitor must connect directly to this pin and the signal return should be kept separate from high-current gate-driver paths.
10	OUTPUT	output	Totem-pole gate driver for the external MOSFET, sourcing and sinking peak currents up to 1 A and held low while VCC is below the turn-on threshold.
11	VC	power_in	Bias supply input for the output gate driver; it must be bypassed by a capacitor at least 10 times the gate capacitance of the main switch FET.
12	VCC	power_in	Supply input for the controller, with recommended supply voltage of 12 V to 28 V and absolute maximum of 30 V from a low-impedance source; it requires a 0.1 µF bypass capacitor to GROUND placed close to the pin.
13	NC	unconnected	Not connected (不连接) in the 14-pin SOIC package.
14	VREF	power_out	5 V reference output that also supplies the oscillator charging current; it requires a ceramic bypass of at least 0.1 µF placed close to the pin, and the recommended reference output current is -20 mA.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-14
Category	Power Management (PMIC)
Pins	14

CAD (KiCad official)

Symbol: UC2843D
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOIC-14 (KiCad packages3D, STEP)
3D model files: uc2843d-etched.step / uc2843d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); uc2843d.step / uc2843d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (61 pp, sha256 0f875fd24cbb5fda, retrieved 2026-10-10, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# UC2843D

**Texas Instruments** · AC-DC Controllers And Regulators · SOIC-14

UC2843D from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier compensation pin: external compensation connects here to shape the error amplifier output, and forcing COMP to GROUND externally sets zero duty cycle; the amplifier has internal current limiting and can source and sink current. |
| 2 | NC | unconnected | Not connected (不连接) in the 14-pin SOIC package. |
| 3 | VFB | input | Inverting input of the internal error amplifier used to close the voltage feedback loop; keep the lead short and stray capacitance low for stability, and the non-inverting reference input is trimmed to 2.5 V. |
| 4 | NC | unconnected | Not connected (不连接) in the 14-pin SOIC package. |
| 5 | ISENSE | input | Primary-side current-sense input to the PWM comparator, connected to the current-sense resistor, which terminates OUTPUT conduction; the sense signal is typically 1 V at maximum and a ramp may be applied for voltage-mode or slope compensation. |
| 6 | NC | unconnected | Not connected (不连接) in the 14-pin SOIC package. |
| 7 | RT/CT | bidirectional | Oscillator timing pin: a timing resistor RT from VREF and timing capacitor CT to GROUND set fOSC = 1.72/(RT×CT); RT must never be below 5 kΩ and CT is recommended between 1 nF and 100 nF. |
| 8 | PWRGND | power_in | Power ground for the high-current output driver stage, kept separate from the analog GROUND so switching currents do not disturb the control circuitry. |
| 9 | GROUND | power_in | Signal and analog ground return for the controller; the timing capacitor must connect directly to this pin and the signal return should be kept separate from high-current gate-driver paths. |
| 10 | OUTPUT | output | Totem-pole gate driver for the external MOSFET, sourcing and sinking peak currents up to 1 A and held low while VCC is below the turn-on threshold. |
| 11 | VC | power_in | Bias supply input for the output gate driver; it must be bypassed by a capacitor at least 10 times the gate capacitance of the main switch FET. |
| 12 | VCC | power_in | Supply input for the controller, with recommended supply voltage of 12 V to 28 V and absolute maximum of 30 V from a low-impedance source; it requires a 0.1 µF bypass capacitor to GROUND placed close to the pin. |
| 13 | NC | unconnected | Not connected (不连接) in the 14-pin SOIC package. |
| 14 | VREF | power_out | 5 V reference output that also supplies the oscillator charging current; it requires a ceramic bypass of at least 0.1 µF placed close to the pin, and the recommended reference output current is -20 mA. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Power Management (PMIC) |
| Pins | 14 |

## CAD (KiCad official)

- Symbol: `UC2843D`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `uc2843d-etched.step` / `uc2843d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `uc2843d.step` / `uc2843d.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/uc3842) (61 pp, sha256 `0f875fd24cbb5fda`, retrieved 2026-10-10, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/uc2843d-datasheet.pdf)