component
UC2842N
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownUC2842N
Texas Instruments · AC-DC Controllers And Regulators · DIP-8
UC2842N from Texas Instruments, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier compensation pin, where external compensation components are connected to modify the error amplifier output, and forcing COMP to GROUND externally sets zero duty cycle because the error amplifier is internally current-limited. |
| 2 | VFB | input | Inverting input of the internal error amplifier used for the voltage feedback loop, where the lead should be kept as short as possible and stray capacitance minimized for stability. |
| 3 | ISENSE | input | Primary-side current sense input to the PWM comparator, connected to the MOSFET current-sense resistor, with a recommended input voltage of 1 V and an absolute maximum analog input of 6.3 V. |
| 4 | RT/CT | bidirectional | Oscillator timing pin, where a timing resistor RT from VREF and a timing capacitor CT to GROUND set fOSC = 1.72/(RRT×CCT), and timing resistors must never be smaller than 5 kΩ. |
| 5 | GROUND | power_in | Analog and signal return ground that should be kept separate from the high-current gate driver return path so signals are not affected by switching current. |
| 6 | OUTPUT | output | Totem-pole gate driver for the external MOSFET that sources and sinks peak currents up to 1 A, and is actively held low when VCC is below the turn-on threshold. |
| 7 | VCC | power_in | Supply input for the controller with a recommended range of 12 V to 28 V and an absolute maximum of 30 V from a low-impedance source, bypassed with at least 0.1 µF directly to GROUND. |
| 8 | VREF | power_out | 5 V reference output that requires at least a 0.1 µF ceramic bypass to GROUND placed close to the pin, with a recommended reference output current of -20 mA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | DIP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
UC2842N - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files:
uc2842n-etched.step/uc2842n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);uc2842n.step/uc2842n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (61 pp, sha256
0f875fd24cbb5fda, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).