# UC2842BN

**lingxingic** · AC-DC Controllers And Regulators · DIP-8

UC2842BN from lingxingic, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier output (comparison terminal) that sets the control voltage; the datasheet's absolute maximum error-amplifier output sink current is 10 mA. |
| 2 | VFB | input | Error amplifier inverting input (negative feedback); the analog input range is -0.3 V to +6.3 V and the input bias current is -2 µA maximum at VFB = 5 V. |
| 3 | ISENSE | input | Current-sense input to the PWM current-sense comparator, with a maximum input signal of 1 V typical (0.9 V to 1.1 V) and input bias current of -10 µA maximum. |
| 4 | RT/CT | passive | Oscillator timing node for the RT/CT network; the datasheet's test condition is RT = 10 kΩ and CT = 3.3 nF, with a discharge current of 7.6 mA to 9 mA at VOSC = 2 V. |
| 5 | GROUND | power_in | Ground reference for the controller, as shown on the pinout. |
| 6 | OUTPUT | output | Push-pull gate-drive output capable of sourcing and sinking large currents for driving MOSFETs, with an output current rating of ±1 A. |
| 7 | Vi | power_in | Supply voltage input with an absolute maximum of 30 V from a low-impedance source, and a minimum operating voltage set by the UVLO thresholds (16 V on / 10 V off for UC2842). |
| 8 | VREF | power_out | 5.00 V reference output (4.90 V to 5.10 V at Io = 1 mA) with a short-circuit current of -30 mA to -180 mA. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | DIP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output current | IO | -1 |  | 1 | A |  | 4 |
| VREF output voltage | VREF | 4.9 | 5 | 5.1 | V | Io=1mA | 5 |
| VREF line regulation | ΔVREF |  | 2 | 20 | mV | 12V≤Vi≤25V | 5 |
| VREF load regulation | ΔVREF |  | 3 | 25 | mV | 1≤Io≤20mA | 5 |
| VREF total output variation |  | 4.7 |  | 5.3 | V | line, load, temperature | 5 |
| Output short-circuit current (printed min -30, typ -100, max -180) | ISC | -30 | -100 | -180 | mA | 注 4 | 5 |
| Oscillator frequency | fOSC | 49 | 52 | 55 | kHz | Tj=25℃ | 5 |
| Oscillator frequency over temperature | fOSC | 48 |  | 56 | kHz | Tamb=Tlow to Thigh | 5 |
| Oscillator frequency (RT=6.2kΩ, CT=1nF) | fOSC | 225 | 250 | 275 | kHz | Tj=25℃ (RT=6.2kΩ，CT=1nF) | 5 |
| Frequency voltage stability | ΔfOSC/ΔV |  | 0.2 | 1 | % | Vi=12V～25V | 5 |
| Oscillator discharge current | Idischg | 7.6 | 8.3 | 9 | mA | VOSC=2V; Tj=25℃，Tamb=-40～105℃ | 5 |
| Error amplifier input voltage | V2 | 2.42 | 2.5 | 2.58 | V | VPIN1=2.5V | 5 |
| Error amplifier input bias current | Ib |  | -0.1 | -2 | uA | VFB=5V | 5 |
| Open-loop voltage gain | AVOL | 65 | 90 |  | dB | 2V≤Vo≤4V | 6 |
| Unity-gain bandwidth | BW | 0.7 | 1 |  | MHz | Tj=25℃ (注 4) | 6 |
| Power supply rejection ratio (error amp) | PSRR | 60 | 70 |  | dB | 12V≤Vi≤25V | 6 |
| Output sink current | IO | 2 | 12 |  | mA | VPIN2=2.7V，VPIN1=1.1V | 6 |
| Output source current | IO | -0.5 | -1 |  | mA | VPIN2=2.3V，VPIN1=5V | 6 |
| Output high level (VOUT High) | VOUT | 5 | 6.2 |  | V | VPIN2=2.3V；RL=15KΩ to ground | 6 |
| Output low level (VOUT Low) | VOUT |  | 0.8 | 1.1 | V | VPIN2=2.7V；RL=15KΩ to PIN 8 | 6 |
| Current sense gain | GV | 2.85 | 3 | 3.15 | V/V | 注 5、6 | 6 |
| Maximum input signal | V3 | 0.9 | 1 | 1.1 | V | VPIN1=5V（注 5） | 6 |
| Current sense power supply rejection ratio | SVR |  |  | 70 | dB | 12V≤Vi≤25V（注 5） | 6 |
| Current sense input bias current | Ib |  | -2 | -10 | uA |  | 6 |
| Propagation delay |  |  | 150 | 300 | ns | 注 4 | 6 |
| Output low level (VOL) | VOL |  | 0.1 | 0.4 | V | Isink=20mA | 6 |
| Output low level (VOL) | VOL |  | 1.6 | 2.2 | V | Isink=200mA | 6 |
| Output high level (VOH) | VOH | 13 | 13.5 |  | V | Isource=20mA | 6 |
| Output high level (VOH) | VOH | 12 | 13.5 |  | V | Isource=200mA | 6 |
| UVLO saturation voltage (VOLS) | VOLS |  | 0.1 | 1.1 | V | Vi=6V，ISINK=1mA | 6 |
| Output rise time | tr |  | 50 | 150 | ns | CL=1nF（注 4） | 6 |
| Output fall time | tf |  | 50 | 150 | ns | CL=1nF（注 4） | 6 |
| UVLO turn-on threshold (UC2842) | VTH(ST) | 14.5 | 16 | 17.5 | V |  | 6 |
| UVLO minimum operating voltage (UC2842) | VOPR(MIN) | 8.5 | 10 | 11.5 | V |  | 6 |
| Maximum duty cycle (UC2842) |  | 95 | 97 | 100 | % |  | 6 |
| Minimum duty cycle |  | 0 |  |  | % |  | 6 |
| Startup current | Ist |  | 0.3 | 0.9 | mA |  | 6 |
| Operating supply current | Ii |  | 12 | 20 | mA | VPIN2=VPIN3=0V | 6 |
| Zener voltage | Viz | 30 | 36 |  | V | Ii=25mA | 6 |

## CAD (KiCad official)

- Symbol: `UC2842BN`
- Footprint: `Package_DIP:DIP-8_W7.62mm`
- 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files: `uc2842bn-etched.step` / `uc2842bn-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `uc2842bn.step` / `uc2842bn.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [lingxingic datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603344870128447488) (11 pp, sha256 `bfa88c81aaa5bbb5`, retrieved 2026-10-15, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/uc2842bn-datasheet.pdf)