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docs uc2842bd1r2g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json uc2842bd1r2g: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md uc2842bd1r2g: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray
uc2842bd1r2g-etched.fit.json uc2842bd1r2g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
uc2842bd1r2g-etched.glb uc2842bd1r2g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
uc2842bd1r2g-etched.step uc2842bd1r2g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
uc2842bd1r2g.glb Publish 0.1.0 · Ray
uc2842bd1r2g.kicad_mod Publish 0.1.0 · Ray
uc2842bd1r2g.kicad_sym Publish 0.1.0 · Ray
uc2842bd1r2g.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
uc2842bd1r2g.step Publish 0.1.0 · Ray

UC2842BD1R2G

onsemi · AC-DC Controllers and Regulators · SOIC-8

UC2842BD1R2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Compensation output Error amplifier output; typically connected via compensation network back to pin 2 (Voltage Feedback) to set loop response. Also serves as the input to the PWM comparator internally. Voltage range 0 to 7.2 V max.
2 Voltage Feedback input Inverting input of the error amplifier. Normally connected through a resistor divider to the converter output for regulation; nominal reference at this pin is 2.5 V. Input voltage range -0.3 to +5.5 V.
3 Current Sense input Non-inverting input of the current sense comparator; senses the primary switch current via a shunt resistor. Cycle-by-cycle current limiting threshold is nominally 1.0 V. Input voltage range -0.3 to +5.5 V.
4 RT/CT passive Oscillator timing pin. Connect a timing resistor (RT) from Vref to this pin and a timing capacitor (CT) from this pin to GND to set the oscillator frequency (guaranteed to 250 kHz, operable to 500 kHz).
5 GND power_in Signal and power ground reference for the device. In the SOIC-8 package this is the single common ground (SOIC-14 splits it into separate signal GND and Power Ground).
6 Output output High-current totem-pole PWM gate-drive output for a power MOSFET. Peak output current 1.0 A source or sink; typical rise/fall time 50 ns into 1.0 nF. Output swings between GND and VCC.
7 VCC power_in Positive supply input for control logic and the output stage. UCX842B startup UVLO threshold is 16 V (typ) with 10 V (typ) minimum operating voltage after turn-on. Absolute maximum 30 V; internal zener clamps at ~36 V.
8 Vref power_out Buffered 5.0 V reference output (trimmed, 5.0 V ±1% at 1 mA), used to bias the oscillator timing network and can supply modest external loads. Short-circuit current limited (-30 to -180 mA).

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category PMIC
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • UC2842BD1R2G
  • UC2842BD1R2GD1G
  • UC2842BD1R2GN
  • UC2842BD1R2GNG
  • UC2842BD1R2GD
  • UC2842BD1R2GDG
  • UC2842BD1R2GDR2G

CAD (KiCad official)

  • Symbol: UC2842BD1R2G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: uc2842bd1r2g-etched.step / uc2842bd1r2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); uc2842bd1r2g.step / uc2842bd1r2g.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
uc2842bd1r2g.step 122 KB You want the bare part, or you mark your own boards.
uc2842bd1r2g-etched.step 2.8 MB You want the part with UC2842BD1R2G already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 662 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (22 pp, sha256 581ae31fbd1f3e07, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF