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UC2842BD

Public Made by Adom

by adom

lingxingic AC-DC Controllers And Regulators, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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UC2842BD

lingxingic · AC-DC Controllers And Regulators · SOP-8

UC2842BD from lingxingic, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 COMP output Error amplifier output and compensation node, with an absolute-maximum error amplifier output sink current of 10 mA.
2 VFB input Negative-feedback (inverting) input of the error amplifier, which regulates to 2.50 V typical (2.42 V to 2.58 V) with an input bias current of -2 µA maximum.
3 ISENSE input Current-sense comparator input with a maximum input signal of 1 V typical (0.9 V to 1.1 V) and a current-sense gain of 3 V/V typical.
4 RT/CT passive Oscillator timing node for the external RT and CT network; the electrical characteristics are specified with RT = 10 kΩ and CT = 3.3 nF, and the device is rated for operating frequencies up to 500 kHz.
5 GROUND power_in Ground reference and common return for the controller circuits.
6 OUTPUT output Push-pull gate drive output for MOSFET power devices, rated for ±1 A output current.
7 Vi power_in Supply voltage input, with an absolute-maximum rating of 30 V from a low-impedance source and a 12 V to 25 V range used in the electrical tests.
8 VREF power_out Internal 5.00 V reference output (4.90 V to 5.10 V at Io = 1 mA, Tj = 25 °C) with a short-circuit current of -30 mA to -180 mA.

Key specifications

Parameter Value
Manufacturer lingxingic
Package SOP-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply voltage (low-impedance source) Vi 30 V 6
Output current IO -1 1 A 6
Error amplifier output sink current Isink(EA) 10 mA 6
Analog input range Vin(EA) -0.3 6.3 V 6
Thermal resistance junction-to-ambient, SOP8 θJA 160 ℃/W Notes 1, 2 (JEDEC 2S2P) 6
Operating temperature Tamb -40 125 ℃ 6
Storage temperature Tstg -65 150 ℃ 6
Soldering temperature, SOP8 TL 260 ℃ 10 s 6
VREF output voltage VREF 4.9 5 5.1 V Io=1mA, Tj=25℃ 6
Line regulation ∆VREF 2 20 mV 12V≤Vi≤25V 6
Load regulation ∆VREF 3 25 mV 1≤Io≤20mA 6
Total output variation 4.7 5.3 V line, load, temperature 6
Output short-circuit current ISC -30 -100 -180 mA Note 4 6
Oscillator frequency fOSC 49 52 55 kHz Tj=25℃ 6
Oscillator frequency over temperature fOSC 47 57 kHz Tamb=-40~125℃ 6
Oscillator frequency with timing components fOSC 225 250 275 kHz Tj=25℃, RT=6.2kΩ, CT=1nF 6
Frequency voltage stability ∆fOSC/∆V 0.2 1 % Vi=12V~25V 6
Discharge current Idischg 7.6 8.3 9 mA VOSC=2V, Tj=25℃ 6
Error amplifier input voltage V2 2.42 2.5 2.58 V VPIN1=2.5V 6
Error amplifier input bias current Ib -0.1 -2 uA VFB=5V 6
Open-loop voltage gain AVOL 65 90 dB 2V≤Vo≤4V 6
Unity-gain bandwidth BW 0.7 1 MHz Tj=25℃, Note 4 6
Power supply rejection ratio (error amp) PSRR 60 70 dB 12V≤Vi≤25V 7
Output sink current IO 2 12 mA VPIN2=2.7V, VPIN1=1.1V 7
Output source current IO -0.5 -1 mA VPIN2=2.3V, VPIN1=5V 7
Output high level (VOUT High) VOUT High 5 6.2 V VPIN2=2.3V; RL=15kΩ to ground 7
Output low level (VOUT Low) VOUT Low 0.8 1.1 V VPIN2=2.7V; RL=15kΩ to PIN 8 7
Current sense gain GV 2.85 3 3.15 V/V Notes 5, 6 7
Maximum input signal V3 0.9 1 1.1 V VPIN1=5V, Note 5 7
Current sense power supply rejection ratio SVR 70 dB 12V≤Vi≤25V, Note 5 7
Current sense input bias current Ib -2 -10 uA 7
Propagation delay 150 300 ns Note 4 7
Output low level, Isink=20mA VOL 0.1 0.4 V Isink=20mA 7
Output low level, Isink=200mA VOL 1.6 2.2 V Isink=200mA 7
Output high level, Isource=20mA VOH 13 13.5 V Isource=20mA 7
Output high level, Isource=200mA VOH 12 13.5 V Isource=200mA 7
Undervoltage lockout saturation voltage VOLS 0.1 1.1 V Vi=6V, ISINK=1mA 7
Output rise time tr 50 150 ns CL=1nF, Note 4 7
Output fall time tf 50 150 ns CL=1nF, Note 4 7
UVLO turn-on threshold (UC2842/UC2844 variant, 16 V) VTH(ST) 14.5 16 17.5 V 7
UVLO minimum operating voltage (UC2842/UC2844 variant, 10 V) VOPR(MIN) 8.5 10 11.5 V 7
Maximum duty cycle 95 97 100 % 7
Minimum duty cycle 0 % 7
Start-up current Ist 0.3 1 mA 7
Operating supply current Ii 12 20 mA VPIN2=VPIN3=0V 7
Zener clamp voltage Viz 30 36 V Ii=25mA 7

CAD (KiCad official)

  • Symbol: UC2842BD
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: uc2842bd-etched.step / uc2842bd-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); uc2842bd.step / uc2842bd.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (11 pp, sha256 065498dc909cbc66, retrieved 2026-10-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF