# UC2842ADTR

**Texas Instruments** · AC-DC Controllers And Regulators · SOIC-14

UC2842ADTR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Output of the low-impedance 1MHz internal error amplifier (80dB open-loop gain) and input to the peak current limit/PWM comparator, with a maximum sink current of 6mA and no internal current limit. |
| 2 | NC | unconnected | No connection. |
| 3 | FB | input | Error amplifier input used to close the converter voltage feedback loop for stability. |
| 4 | NC | unconnected | No connection. |
| 5 | ISENSE | input | Input to the peak current limit/PWM comparator, used with a current-sense resistor, with the maximum peak current-sense signal clamped internally to 1V. |
| 6 | NC | unconnected | No connection. |
| 7 | RT/CT | input | Internal oscillator input programmed by an external timing resistor RT and capacitor CT, with 470pF to 4.7nF for CT and 5kΩ to 100kΩ for RT recommended. |
| 8 | PGND | power_in | Power ground and gate-driver return path, allowing star grounding to steer gate-driver current away from the signal ground pin GND. |
| 9 | GND | power_in | Controller signal ground. |
| 10 | OUTPUT | output | Output of the 1A totem-pole gate driver, sourcing/sinking up to 1A, requiring a gate-driver resistor to limit current. |
| 11 | VC | power_in | Gate-driver bias input requiring a bias capacitor at least 10 times larger than the gate capacitance of the main switching FET. |
| 12 | VCC | power_in | Bias supply input requiring a bias capacitor at least 10 times larger than the gate capacitance of the main switching FET. |
| 13 | NC | unconnected | No connection. |
| 14 | VREF | power_out | 5V reference output supplying up to 10mA in normal operation, short-circuit protected at about 100mA, requiring a 1µF high-frequency bypass capacitor. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Power Management (PMIC) |
| Pins | 14 |

## CAD (KiCad official)

- Symbol: `UC2842ADTR`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `uc2842adtr-etched.step` / `uc2842adtr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `uc2842adtr.step` / `uc2842adtr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/uc2845a) (54 pp, sha256 `1f5ad8805f414728`, retrieved 2026-10-06, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/uc2842adtr-datasheet.pdf)