component
UC2825AQDWREP
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownUC2825AQDWREP
Texas Instruments · DC-DC Converters · SOIC-16-300mil
UC2825AQDWREP from Texas Instruments, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | INV | input | Inverting input to the error amplifier. |
| 2 | NI | input | Noninverting input to the error amplifier. |
| 3 | EAOUT | output | Output of the error amplifier for compensation; the datasheet limits its output current to 5 mA maximum (absolute maximum). |
| 4 | CLK/LEB | output | Clock/leading-edge blanking pin, the buffered output of the internal oscillator; clock output current is limited to -5 mA in the absolute maximum ratings. |
| 5 | RT | input | Resistor timing connection for oscillator frequency programming; recommended RT values range from 1 kΩ to 100 kΩ. |
| 6 | CT | input | Capacitor timing connection for oscillator frequency programming, which should be connected to device ground using minimal trace length. |
| 7 | RAMP | input | Noninverting input to the PWM comparator with 1.25-V internal input offset, used for voltage-mode feed-forward or as the peak-current-mode slope compensation input. |
| 8 | SS | input | Soft-start pin that also doubles as the maximum duty cycle clamp; soft-start sink current is limited to 20 mA maximum. |
| 9 | ILIM | input | Input to the current-limit comparator; the current-limit threshold is 1 V and the overcurrent (fault) threshold is 1.2 V. |
| 10 | GND | power_in | Analog ground return for the control circuitry. |
| 11 | OUTA | output | High-current totem-pole output A of the on-chip drive stage, rated for 2-A peak current and limited to outputs between PGND -0.3 V and VC +0.3 V. |
| 12 | PGND | power_in | Ground return for the output driver stage, which should be kept separate from analog ground in layout. |
| 13 | VC | power_in | Power supply for the output stage, with a 22-V absolute maximum supply rating (VC, VCC), to be bypassed with a 0.1 µF low-ESL ceramic capacitor placed with minimal trace lengths. |
| 14 | OUTB | output | High-current totem-pole output B of the on-chip drive stage, rated for 2-A peak current and limited to outputs between PGND -0.3 V and VC +0.3 V. |
| 15 | VCC | power_in | Power supply for the device, with a 22-V absolute maximum rating (VC, VCC), to be bypassed with a 0.1 µF low-ESL ceramic capacitor placed with minimal trace lengths. |
| 16 | VREF | power_out | 5.1-V reference output, to be bypassed with a 0.1 µF low-ESL ceramic capacitor and minimal trace length to the ground plane for stability. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16-300mil |
| Category | Power Management (PMIC) |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
UC2825AQDWREP - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files:
uc2825aqdwrep-etched.step/uc2825aqdwrep-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);uc2825aqdwrep.step/uc2825aqdwrep.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
e4dae8b70863cbf0, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).