component
UC1843AMDREP
Public Made by Adomby adom
Texas Instruments AC-DC Controllers and Regulators, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
main
UC1843AMDREP
Texas Instruments · AC-DC Controllers and Regulators · SOIC-8
UC1843AMDREP from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier output / compensation node. Connect frequency-compensation network between this pin and VFB. Also serves as the control-loop input to the PWM comparator. |
| 2 | VFB | input | Inverting input to the error amplifier. Normally connected via a resistor divider to the converter output; the non-inverting input is internally tied to the 2.50 V reference. Absolute max input range -0.3 V to 6.3 V. |
| 3 | ISENSE | input | Current-sense input to the PWM current-sense comparator. Internal 1 V clamp provides pulse-by-pulse current limiting. Typical gain 3 V/V; input bias current ~-2 uA; absolute max range -0.3 V to 6.3 V. |
| 4 | RT/CT | passive | Oscillator timing pin. Connect a timing resistor from VREF to RT/CT and a timing capacitor from RT/CT to GND to set the switching frequency (up to 500 kHz). Oscillator discharge current trimmed to ~8.3 mA. |
| 5 | GND | power_in | Device ground / power ground return. All internal reference voltages are referenced to this pin. |
| 6 | OUTPUT | output | High-current totem-pole gate-drive output for driving an external power MOSFET. Rated for +/-1 A peak; typical rise/fall time 50 ns into 1 nF load; high-level output 13.5 V typical with 20 mA source. |
| 7 | VCC | power_in | Positive supply input for the IC and output driver. UVLO start threshold 8.4 V typ, turn-off 7.6 V typ (UC1843A). Low start-up current <0.5 mA. Internal 34 V zener clamp; absolute max low-impedance source 30 V. |
| 8 | VREF | power_out | Trimmed 5.0 V internal bandgap reference output, capable of sourcing up to 50 mA. Typically used to bias the oscillator timing network and external circuitry. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | PMIC |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
UC1843AMDREP
CAD (KiCad official)
- Symbol:
UC1843AMDREP - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
uc1843amdrep-etched.step/uc1843amdrep-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);uc1843amdrep.step/uc1843amdrep.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (17 pp, sha256
53c59033a3dd0a96, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# UC1843AMDREP
**Texas Instruments** · AC-DC Controllers and Regulators · SOIC-8
UC1843AMDREP from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier output / compensation node. Connect frequency-compensation network between this pin and VFB. Also serves as the control-loop input to the PWM comparator. |
| 2 | VFB | input | Inverting input to the error amplifier. Normally connected via a resistor divider to the converter output; the non-inverting input is internally tied to the 2.50 V reference. Absolute max input range -0.3 V to 6.3 V. |
| 3 | ISENSE | input | Current-sense input to the PWM current-sense comparator. Internal 1 V clamp provides pulse-by-pulse current limiting. Typical gain 3 V/V; input bias current ~-2 uA; absolute max range -0.3 V to 6.3 V. |
| 4 | RT/CT | passive | Oscillator timing pin. Connect a timing resistor from VREF to RT/CT and a timing capacitor from RT/CT to GND to set the switching frequency (up to 500 kHz). Oscillator discharge current trimmed to ~8.3 mA. |
| 5 | GND | power_in | Device ground / power ground return. All internal reference voltages are referenced to this pin. |
| 6 | OUTPUT | output | High-current totem-pole gate-drive output for driving an external power MOSFET. Rated for +/-1 A peak; typical rise/fall time 50 ns into 1 nF load; high-level output 13.5 V typical with 20 mA source. |
| 7 | VCC | power_in | Positive supply input for the IC and output driver. UVLO start threshold 8.4 V typ, turn-off 7.6 V typ (UC1843A). Low start-up current <0.5 mA. Internal 34 V zener clamp; absolute max low-impedance source 30 V. |
| 8 | VREF | power_out | Trimmed 5.0 V internal bandgap reference output, capable of sourcing up to 50 mA. Typically used to bias the oscillator timing network and external circuitry. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | PMIC |
| Pins | 8 |
## Ordering variants
Same part, different packaging or reel option.
- `UC1843AMDREP`
## CAD (KiCad official)
- Symbol: `UC1843AMDREP`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `uc1843amdrep-etched.step` / `uc1843amdrep-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `uc1843amdrep.step` / `uc1843amdrep.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](docs/uc1843amdrep-datasheet.pdf) (17 pp, sha256 `53c59033a3dd0a96`, retrieved 2026-08-17, tier: lcsc)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/uc1843amdrep-datasheet.pdf)