component
UA78L05ACPKM3
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-89-3. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownUA78L05ACPKM3
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-89-3
UA78L05ACPKM3 from Texas Instruments, in a SOT-89-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUTPUT | power_out | Regulated 5 V output; use the recommended output capacitor of 0.1 µF from the Recommended Operating Conditions table and place it as close to the OUT and GND pins as possible. |
| 2 | COMMON | power_in | Ground (common) reference pin for the regulator. |
| 3 | INPUT | input | Input pin for the UA78L05AC, recommended input voltage 7 V to 20 V; use the recommended input capacitor of 0.33 µF and place it as close to the IN and GND pins as possible. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-89-3 |
| Category | Power Management (PMIC) |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage (absolute maximum, new chip) | VI | 45 | V | New chip; UA78L05AC listed | 4 | ||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Input voltage (recommended) | VI | 7 | 20 | V | UA78L05C and UA78L05AC, legacy and new chip | 4 | |
| Output current | IO | 100 | mA | 4 | |||
| Operating junction temperature | TJ | -40 | 125 | °C | UA78L00C, UA78L00AC and UA78L05AI series, new chip | 4 | |
| Output voltage | 4.95 | 5 | 5.15 | V | VI = 7 V to 20 V, IO = 1 mA to 40 mA, TJ = 25°C (new chip) | 6 | |
| Output voltage | 4.85 | 5.15 | V | VI = 7 V to 20 V, IO = 1 mA to 40 mA, TJ = full range (new chip) | 6 | ||
| Output voltage | 4.8 | 5.14 | V | IO = 1 mA to 70 mA, TJ = full range (new chip) | 6 | ||
| Input voltage regulation | 32 | 33 | mV | VI = 7 V to 20 V, TJ = 25°C (new chip) | 6 | ||
| Input voltage regulation | 26 | 28 | mV | VI = 8 V to 20 V, TJ = 25°C (new chip) | 6 | ||
| Ripple rejection | 48 | 55 | dB | VI = 8 V to 18 V, f = 120 Hz, TJ = 25°C (new chip) | 6 | ||
| Output voltage regulation | 15 | 35 | mV | IO = 1 mA to 100 mA, TJ = 25°C (new chip) | 6 | ||
| Output voltage regulation | 8 | 15 | mV | IO = 1 mA to 40 mA, TJ = 25°C (new chip) | 6 | ||
| Bias current | 3.53 | 3.95 | mA | TJ = 25°C (new chip) | 7 | ||
| Output noise voltage | 125 | µV | f = 10 Hz to 100 kHz, TJ = 25°C (new chip) | 6 | |||
| Dropout voltage | 1.7 | V | TJ = 25°C (new chip) | 6 | |||
| Bias current | 4 | mA | TJ = 125°C (new chip) | 7 | |||
| Bias current change | 0.485 | mA | VI = 8 V to 20 V, TJ = full range (new chip) | 7 | |||
| Bias current change | 0.01 | mA | IO = 1 mA to 40 mA, TJ = full range (new chip) | 7 | |||
| Junction-to-ambient thermal resistance | RθJA | 54.7 | °C/W | PK (SOT-89) package | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 88.1 | °C/W | PK (SOT-89) package | 5 | ||
| Junction-to-board thermal resistance | RθJB | 9.6 | °C/W | PK (SOT-89) package | 5 | ||
| Junction-to-top characterization parameter | ψJT | 6.2 | °C/W | PK (SOT-89) package | 5 | ||
| Junction-to-board characterization parameter | ψJB | 9.7 | °C/W | PK (SOT-89) package | 5 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 7.7 | °C/W | PK (SOT-89) package | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | Keep trace widths large enough to eliminate problematic I×R voltage drops at the input and output pins. Place bypass capacitors as close to the UA78L as possible. Additional copper and vias connected | 26 |
CAD (KiCad official)
- Symbol:
UA78L05ACPKM3 - Footprint:
Package_TO_SOT_SMD:SOT-89-3 - 3D model: SOT-89-3 (KiCad packages3D, STEP)
- 3D model files:
ua78l05acpkm3-etched.step/ua78l05acpkm3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ua78l05acpkm3.step/ua78l05acpkm3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (47 pp, sha256
a1ac403ce6d0e41e, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).