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U74HC4060G-S16-R

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UTC Unisonic Tech Counters, Dividers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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U74HC4060G-S16-R

UTC Unisonic Tech · Counters, Dividers · SOP-16

U74HC4060G-S16-R from UTC Unisonic Tech, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 QL output Buffered binary counter output QL; it is driven low by the asynchronous master reset (CLR high) and the datasheet rates the outputs to drive up to 10 LSTTL loads.
2 QM output Buffered binary counter output QM; it is driven low by the asynchronous master reset (CLR high) and the datasheet rates the outputs to drive up to 10 LSTTL loads.
3 QN output Buffered binary counter output QN; it is driven low by the asynchronous master reset (CLR high) and the datasheet rates the outputs to drive up to 10 LSTTL loads.
4 QF output Buffered binary counter output QF; it is driven low by the asynchronous master reset (CLR high) and the datasheet rates the outputs to drive up to 10 LSTTL loads.
5 QE output Buffered binary counter output QE; it is driven low by the asynchronous master reset (CLR high) and the datasheet rates the outputs to drive up to 10 LSTTL loads.
6 QG output Buffered binary counter output QG; it is driven low by the asynchronous master reset (CLR high) and the datasheet rates the outputs to drive up to 10 LSTTL loads.
7 QD output Buffered binary counter output QD; it is driven low by the asynchronous master reset (CLR high) and the datasheet rates the outputs to drive up to 10 LSTTL loads.
8 GND power_in Ground reference for the device.
9 CLKO passive Oscillator terminal for an RC or crystal oscillator network; it is left floating when the oscillator is replaced by an external clock on CLKI.
10 CLKO passive Second oscillator terminal for an RC or crystal oscillator network; it is left floating when the oscillator is replaced by an external clock on CLKI.
11 CLKI input Oscillator input or external clock input; the counter advances on the negative-going transition of CLKI.
12 CLR input Asynchronous master reset; a high level disables the oscillator and resets all Q outputs low, and the datasheet gives a CLR-to-CLKI setup time of 200 ns at 2.0 V, 40 ns at 4.5 V and 34 ns at 6.0 V.
13 QI output Buffered binary counter output QI; it is driven low by the asynchronous master reset (CLR high) and the datasheet rates the outputs to drive up to 10 LSTTL loads.
14 QH output Buffered binary counter output QH; it is driven low by the asynchronous master reset (CLR high) and the datasheet rates the outputs to drive up to 10 LSTTL loads.
15 QJ output Buffered binary counter output QJ; it is driven low by the asynchronous master reset (CLR high) and the datasheet rates the outputs to drive up to 10 LSTTL loads.
16 VCC power_in Positive supply pin; the recommended operating supply range is 2.0 V to 6.0 V.

Key specifications

Parameter Value
Manufacturer UTC Unisonic Tech
Package SOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC -0.5 7 V 5
Input Clamp Current IIK -20 20 mA VI<0 or VI>VCC 5
Output Clamp Current IOK -20 20 mA VO<0 or VO>VCC 5
VCC or GND Current ICC -50 50 mA 5
Continuous Output Current IOUT -25 25 mA VO=0 to VCC 5
Storage Temperature TSTG -65 150 °C 5
Supply Voltage VCC 2 6 V Operating 5
Input Voltage VIN 0 V 5
Output Voltage VOUT 0 V 5
Input Rise or Fall Times tR, tF 1000 ns VCC=2.0V 5
Input Rise or Fall Times tR, tF 500 ns VCC=4.5V 5
Input Rise or Fall Times tR, tF 400 ns VCC=6.0V 5
Operating Temperature TA -40 125 °C 5
High-Level Input Voltage VIH 1.5 V VCC=2V 5
High-Level Input Voltage VIH 3.15 V VCC=4.5V 5
High-Level Input Voltage VIH 4.2 V VCC=6V 5
Low-Level Input Voltage VIL 0.5 V VCC=2V 5
Low-Level Input Voltage VIL 1.35 V VCC=4.5V 5
Low-Level Input Voltage VIL 1.8 V VCC=6V 5
High-Level Output Voltage VOH 1.9 1.998 V VCC=2V, IOH=-20μA 5
High-Level Output Voltage VOH 4.4 4.499 V VCC=4.5V, IOH=-20μA 5
High-Level Output Voltage VOH 5.9 5.999 V VCC=6V, IOH=-20μA 5
High-Level Output Voltage VOH 3.98 4.3 V VCC=4.5V, IOH=-4.0mA 5
High-Level Output Voltage VOH 5.48 5.8 V VCC=6V, IOH=-5.2mA 5
Low-Level Output Voltage VOL 0.002 0.1 V VCC=2V, IOL=20μA 5
Low-Level Output Voltage VOL 0.001 0.1 V VCC=4.5V, IOL=20μA 5
Low-Level Output Voltage VOL 0.17 0.26 V VCC=4.5V, IOL=4mA 5
Low-Level Output Voltage VOL 0.15 0.26 V VCC=6V, IOL=5.2mA 5
Input Leakage Current II(LEAK) -100 100 nA VCC=6V, VIN= VCC or GND 5
Quiescent Supply Current ICC 8 μA VCC=6V, VIN=VCC or GND, IOUT=0 5
Clock Frequency fclock 4.3 MHz VCC=2V 6
Clock Frequency fclock 22 MHz VCC=4.5V 6
Clock Frequency fclock 25 MHz VCC=6V 6
Pulse Duration CLKI high or low tW 115 ns VCC=2V 6
Pulse Duration CLKI high or low tW 23 ns VCC=4.5V 6
Pulse Duration CLKI high or low tW 20 ns VCC=6V 6
Pulse Duration CLR high tW 115 ns VCC=2V 6
Pulse Duration CLR high tW 23 ns VCC=4.5V 6
Pulse Duration CLR high tW 20 ns VCC=6V 6
Setup time, CLR Inactive Before CLKI High To Low tsu 200 ns VCC=2V 6
Setup time, CLR Inactive Before CLKI High To Low tsu 40 ns VCC=4.5V 6
Setup time, CLR Inactive Before CLKI High To Low tsu 34 ns VCC=6V 6
Maximum Clock Pulse Frequency fMAX 4.3 MHz VCC=2V, CL=50pF 6
Maximum Clock Pulse Frequency fMAX 22 MHz VCC=4.5V, CL=50pF 6
Maximum Clock Pulse Frequency fMAX 25 MHz VCC=6V, CL=50pF 6
Propagation delay from CLKI to QD tPD 615 ns VCC=2V, CL=50pF 6
Propagation delay from CLKI to QD tPD 123 ns VCC=4.5V, CL=50pF 6
Propagation delay from CLKI to QD tPD 105 ns VCC=6V, CL=50pF 6
Propagation delay from CLR to Any Q tPHL 175 ns VCC=2V, CL=50pF 6
Propagation delay from CLR to Any Q tPHL 35 ns VCC=4.5V, CL=50pF 6
Propagation delay from CLR to Any Q tPHL 30 ns VCC=6V, CL=50pF 6
Output rise or fall time tt 95 ns VCC=2V, CL=50pF 6
Output rise or fall time tt 19 ns VCC=4.5V, CL=50pF 6
Output rise or fall time tt 16 ns VCC=6V, CL=50pF 6
Power Dissipation Capacitance CPD 88 pF No load 6

CAD (KiCad official)

  • Symbol: U74HC4060G-S16-R
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: u74hc4060g-s16-r-etched.step / u74hc4060g-s16-r-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); u74hc4060g-s16-r.step / u74hc4060g-s16-r.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: UTC Unisonic Tech datasheet (7 pp, sha256 858b4e72f53cee38, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF