component
U74ACT08G
Public Made by Adomby adom
UTC Unisonic Tech Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
U74ACT08G
UTC Unisonic Tech · Logic Gates · SOP-14
U74ACT08G from UTC Unisonic Tech, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Input A of gate 1; the gate implements Y = A·B, and the inputs are TTL-compatible. |
| 2 | 1B | input | Input B of gate 1; the gate implements Y = A·B, and the inputs are TTL-compatible. |
| 3 | 1Y | output | Output of gate 1 (Y = A·B); output current is limited to ±50 mA absolute maximum. |
| 4 | 2A | input | Input A of gate 2; the gate implements Y = A·B, and the inputs are TTL-compatible. |
| 5 | 2B | input | Input B of gate 2; the gate implements Y = A·B, and the inputs are TTL-compatible. |
| 6 | 2Y | output | Output of gate 2 (Y = A·B); output current is limited to ±50 mA absolute maximum. |
| 7 | GND | power_in | Ground reference pin for the device. |
| 8 | 3Y | output | Output of gate 3 (Y = A·B); output current is limited to ±50 mA absolute maximum. |
| 9 | 3A | input | Input A of gate 3; the gate implements Y = A·B, and the inputs are TTL-compatible. |
| 10 | 3B | input | Input B of gate 3; the gate implements Y = A·B, and the inputs are TTL-compatible. |
| 11 | 4Y | output | Output of gate 4 (Y = A·B); output current is limited to ±50 mA absolute maximum. |
| 12 | 4A | input | Input A of gate 4; the gate implements Y = A·B, and the inputs are TTL-compatible. |
| 13 | 4B | input | Input B of gate 4; the gate implements Y = A·B, and the inputs are TTL-compatible. |
| 14 | VCC | power_in | Positive supply; recommended operating range is 4.5 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UTC Unisonic Tech |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | -0.5 | 7 | V | 3 | ||
| Input Voltage | VIN | -0.5 | V | 3 | |||
| DC Output Voltage | VOUT | -0.5 | V | 3 | |||
| Input Clamp Current (VIN<0) | IIK | -20 | 20 | mA | 3 | ||
| Output Clamp Current (VOUT<0) | IOK | -20 | 20 | mA | 3 | ||
| Output Current | IOUT | -50 | 50 | mA | 3 | ||
| VCC or GND Current | ICC | -200 | 200 | mA | 3 | ||
| Storage Temperature | TSTG | -65 | 150 | °C | 3 | ||
| Supply Voltage | VCC | 4.5 | 5.5 | V | 3 | ||
| Input Voltage | VIN | 0 | V | 3 | |||
| Output Voltage | VOUT | 0 | V | 3 | |||
| Input Transition Rise or Fall Rate | t/v | 8 | ns/V | 3 | |||
| Operating Temperature | TA | -40 | 125 | °C | 3 | ||
| High-Level Input Voltage | VIH | 2 | V | VCC=4.5V~5.5V | 3 | ||
| Low-Level Input Voltage | VIL | 0.8 | V | VCC=4.5V~5.5V | 3 | ||
| High-Level Output Voltage | VOH | 3.86 | V | VCC=4.5V IOH=-24mA | 3 | ||
| High-Level Output Voltage | VOH | 4.4 | 4.49 | V | VCC=4.5V IOH=-50μA | 3 | |
| High-Level Output Voltage | VOH | 4.86 | V | VCC=5.5V IOH=-24mA | 3 | ||
| High-Level Output Voltage | VOH | 5.4 | 5.49 | V | VCC=5.5V IOH=-50μA | 3 | |
| Low-Level Output Voltage | VOL | 0.36 | V | VCC=4.5V IOL=24mA | 3 | ||
| Low-Level Output Voltage | VOL | 0.001 | 0.1 | V | VCC=4.5V IOL=50μA | 3 | |
| Input Leakage Current | II(LEAK) | -0.1 | 0.1 | μA | VCC=5.5V, VIN=5.5V or GND | 3 | |
| Quiescent Supply Current | IQ | 4 | μA | VCC=5.5V, VIN=VCC or GND IOUT=0 | 3 | ||
| Additional Quiescent Supply Current Per Input Pin | ΔIQ | 0.6 | mA | VCC=5.5V, VIN=3.4V; other input at VCC or GND; IOUT=0 | 3 | ||
| Propagation Delay Time | tPLH / tPHL | 1.5 | 5 | 9 | ns | VCC =5.0V±0.5V, CL =50pF, RL =500Ω | 3 |
| Input Capacitance | CIN | 4 | pF | VCC=5.0V, VIN=VCC or GND | 3 | ||
| Power Dissipation Capacitance | CPD | 30 | pF | VCC =5.0V | 3 |
CAD (KiCad official)
- Symbol:
U74ACT08G - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files:
u74act08g-etched.step/u74act08g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);u74act08g.step/u74act08g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: UTC Unisonic Tech datasheet (4 pp, sha256
ec0bb4186cf20e2e, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# U74ACT08G
**UTC Unisonic Tech** · Logic Gates · SOP-14
U74ACT08G from UTC Unisonic Tech, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Input A of gate 1; the gate implements Y = A·B, and the inputs are TTL-compatible. |
| 2 | 1B | input | Input B of gate 1; the gate implements Y = A·B, and the inputs are TTL-compatible. |
| 3 | 1Y | output | Output of gate 1 (Y = A·B); output current is limited to ±50 mA absolute maximum. |
| 4 | 2A | input | Input A of gate 2; the gate implements Y = A·B, and the inputs are TTL-compatible. |
| 5 | 2B | input | Input B of gate 2; the gate implements Y = A·B, and the inputs are TTL-compatible. |
| 6 | 2Y | output | Output of gate 2 (Y = A·B); output current is limited to ±50 mA absolute maximum. |
| 7 | GND | power_in | Ground reference pin for the device. |
| 8 | 3Y | output | Output of gate 3 (Y = A·B); output current is limited to ±50 mA absolute maximum. |
| 9 | 3A | input | Input A of gate 3; the gate implements Y = A·B, and the inputs are TTL-compatible. |
| 10 | 3B | input | Input B of gate 3; the gate implements Y = A·B, and the inputs are TTL-compatible. |
| 11 | 4Y | output | Output of gate 4 (Y = A·B); output current is limited to ±50 mA absolute maximum. |
| 12 | 4A | input | Input A of gate 4; the gate implements Y = A·B, and the inputs are TTL-compatible. |
| 13 | 4B | input | Input B of gate 4; the gate implements Y = A·B, and the inputs are TTL-compatible. |
| 14 | VCC | power_in | Positive supply; recommended operating range is 4.5 V to 5.5 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UTC Unisonic Tech |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | -0.5 | | 7 | V | | 3 |
| Input Voltage | VIN | -0.5 | | | V | | 3 |
| DC Output Voltage | VOUT | -0.5 | | | V | | 3 |
| Input Clamp Current (VIN<0) | IIK | -20 | | 20 | mA | | 3 |
| Output Clamp Current (VOUT<0) | IOK | -20 | | 20 | mA | | 3 |
| Output Current | IOUT | -50 | | 50 | mA | | 3 |
| VCC or GND Current | ICC | -200 | | 200 | mA | | 3 |
| Storage Temperature | TSTG | -65 | | 150 | °C | | 3 |
| Supply Voltage | VCC | 4.5 | | 5.5 | V | | 3 |
| Input Voltage | VIN | 0 | | | V | | 3 |
| Output Voltage | VOUT | 0 | | | V | | 3 |
| Input Transition Rise or Fall Rate | t/v | | | 8 | ns/V | | 3 |
| Operating Temperature | TA | -40 | | 125 | °C | | 3 |
| High-Level Input Voltage | VIH | 2 | | | V | VCC=4.5V~5.5V | 3 |
| Low-Level Input Voltage | VIL | | | 0.8 | V | VCC=4.5V~5.5V | 3 |
| High-Level Output Voltage | VOH | 3.86 | | | V | VCC=4.5V IOH=-24mA | 3 |
| High-Level Output Voltage | VOH | 4.4 | 4.49 | | V | VCC=4.5V IOH=-50μA | 3 |
| High-Level Output Voltage | VOH | 4.86 | | | V | VCC=5.5V IOH=-24mA | 3 |
| High-Level Output Voltage | VOH | 5.4 | 5.49 | | V | VCC=5.5V IOH=-50μA | 3 |
| Low-Level Output Voltage | VOL | | | 0.36 | V | VCC=4.5V IOL=24mA | 3 |
| Low-Level Output Voltage | VOL | | 0.001 | 0.1 | V | VCC=4.5V IOL=50μA | 3 |
| Input Leakage Current | II(LEAK) | -0.1 | | 0.1 | μA | VCC=5.5V, VIN=5.5V or GND | 3 |
| Quiescent Supply Current | IQ | | | 4 | μA | VCC=5.5V, VIN=VCC or GND IOUT=0 | 3 |
| Additional Quiescent Supply Current Per Input Pin | ΔIQ | | | 0.6 | mA | VCC=5.5V, VIN=3.4V; other input at VCC or GND; IOUT=0 | 3 |
| Propagation Delay Time | tPLH / tPHL | 1.5 | 5 | 9 | ns | VCC =5.0V±0.5V, CL =50pF, RL =500Ω | 3 |
| Input Capacitance | CIN | | 4 | | pF | VCC=5.0V, VIN=VCC or GND | 3 |
| Power Dissipation Capacitance | CPD | | 30 | | pF | VCC =5.0V | 3 |
## CAD (KiCad official)
- Symbol: `U74ACT08G`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files: `u74act08g-etched.step` / `u74act08g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `u74act08g.step` / `u74act08g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [UTC Unisonic Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8602990146291978240) (4 pp, sha256 `ec0bb4186cf20e2e`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/u74act08g-datasheet.pdf)