component
U3525L-D16-T
Public Made by Adomby adom
UTC(Unisonic Tech) Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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U3525L-D16-T
UTC(Unisonic Tech) · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DIP-16
U3525L-D16-T from UTC(Unisonic Tech), in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | INV. INPUT | input | Inverting input of the error amplifier, with input bias current of 1 µA typ and 10 µA max and common-mode range of 1.5 to 5.2 V. |
| 2 | N.I. INPUT | input | Non-inverting input of the error amplifier, with input bias current of 1 µA typ and 10 µA max and common-mode range of 1.5 to 5.2 V. |
| 3 | SYNC | input | Separate oscillator sync terminal with a sync threshold of 1.2 to 2.8 V (2 V typ) and sync input current of 1 to 2.5 mA at 3.5 V. |
| 4 | OSC. OUTPUT | output | Oscillator clock output with a clock amplitude of 3 to 3.5 V and a clock width of 0.3 to 1 µs. |
| 5 | CT | passive | Oscillator timing capacitor connection with a recommended range of 0.001 to 0.1 µF. |
| 6 | RT | passive | Oscillator timing resistor connection with a recommended range of 2 to 150 kΩ. |
| 7 | DISCHARGE | passive | Oscillator discharge terminal where a dead time resistor (0 to 500 Ω) to CT sets the dead time. |
| 8 | SOFT-START | passive | Soft-start capacitor connection with a current-source pull-up of 25 to 80 µA, and pulling it down turns off the outputs. |
| 9 | COMP | bidirectional | Error amplifier output/compensation terminal with a current-source pull-up, and pulling it down (about 100 µA) turns off the outputs. |
| 10 | SHUT DOWN | input | Shutdown input with a threshold of 0.6 to 1 V that sets the PWM latch and discharges the soft-start capacitor with a 150 µA sink, and it should not be left floating. |
| 11 | OUTPUT A | output | Totem-pole output A that sources or sinks over 200 mA (500 mA absolute max) and gives a LOW output when off. |
| 12 | GROUND | power_in | Ground reference for the device. |
| 13 | VC | power_in | Collector supply for the output stages, with a recommended range of 4.5 to 35 V and an absolute maximum of 40 V. |
| 14 | OUTPUT B | output | Totem-pole output B that sources or sinks over 200 mA (500 mA absolute max) and gives a LOW output when off. |
| 15 | +VI | power_in | Input supply voltage with a recommended range of 8 to 35 V and an absolute maximum of 40 V. |
| 16 | VREF | power_out | Trimmed 5.1 V reference output (±1%) that supplies up to 20 mA of load current. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UTC(Unisonic Tech) |
| Package | DIP-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | ViN | 40 | V | 4 | |||
| Collector Supply Voltage | VC | 40 | V | 4 | |||
| Oscillator Charging Current | IOSC | 5 | mA | 4 | |||
| Output Current, Source or Sink | Io | 500 | mA | 4 | |||
| Reference Output Current | IR | 50 | mA | 4 | |||
| Current through CT Terminal | IT | 5 | mA | 4 | |||
| Logic Inputs voltage | -0.3 | 5.5 | V | 4 | |||
| Total Power Dissipation | PD | 1000 | mW | Ta = 70 °C | 4 | ||
| Junction Temperature | TJ | -55 | 125 | °C | 4 | ||
| Operating Ambient Temperature | TORP | 0 | 70 | °C | 4 | ||
| Input Voltage | VIN | 8 | 35 | V | 4 | ||
| Collector Supply Voltage | VC | 4.5 | 35 | V | 4 | ||
| Sink/Source Load Current (steady state) | ISTEAD | 0 | 100 | mA | 4 | ||
| Sink/Source Load Current (peak) | IPEAK | 0 | 400 | mA | 4 | ||
| Reference Load Current | ILOAD | 0 | 20 | mA | 4 | ||
| Oscillator Frequency Range | FO | 100 | 400 | KHz | 4 | ||
| Oscillator Timing Resistor | RO | 2 | 150 | KΩ | 4 | ||
| Oscillator Timing Capacitor | CO | 0.001 | 0.1 | μF | 4 | ||
| Dead Time Resistor Range | RT | 0 | 500 | Ω | 4 | ||
| Output Voltage | VREF | 5 | 5.1 | 5.2 | V | TJ = 25°C | 5 |
| Total Output Variation | 4.95 | 5.25 | V | Line, Load and Temperature | 5 | ||
| Line Regulation | △VREF | 10 | 20 | mV | VIN = 8 ~ 35 V | 5 | |
| Load Regulation | △VREF | 20 | 50 | mV | IL = 0 ~ 20 mA | 5 | |
| Temp. Stability | △VREF/△T | 20 | 50 | mV | Over Operating Range | 5 | |
| Short Circuit Current | 80 | 100 | mA | VREF = 0, TJ = 25°C | 5 | ||
| Clock Amplitude | 3 | 3.5 | V | 5 | |||
| Sync Threshold | 1.2 | 2 | 2.8 | V | 5 | ||
| Sync Input Current | 1 | 2.5 | mA | Sync Voltage = 3.5 V | 5 | ||
| Current Mirror | 1.7 | 2 | 2.2 | mA | IRT = 2 mA | 5 | |
| Clock Width | 0.3 | 0.5 | 1 | μs | TJ = 25°C | 5 | |
| Initial Accuracy | -6 | 2 | 6 | % | TJ = 25°C | 5 | |
| Voltage Stability | -2 | 1 | 2 | % | VIN = 8 ~ 35 V | 5 | |
| Temperature Stability | △f/△T | -6 | 3 | 6 | % | Over Operating Range | 5 |
| Output Low Level | 0.2 | 0.5 | V | VCM = 5.1 V | 5 | ||
| Output High Level | 3.8 | 5.6 | V | VCM = 5.1 V | 5 | ||
| Input Offset Voltage | VOS | 2 | 10 | mV | VCM = 5.1 V | 5 | |
| Input Bias Current | Ib | 1 | 10 | μA | VCM = 5.1 V | 5 | |
| Comm. Mode Reject. | CMR | 60 | 75 | dB | VCM = 1.5 ~ 5.2 V | 5 | |
| Supply Voltage Rejection | PSR | 50 | 60 | dB | VIN = 8 ~ 35 V | 5 | |
| DC Open Loop Gain | 60 | 75 | dB | RL ≥ 10 MΩ | 5 | ||
| DC Transconduct. | 1.1 | 1.5 | ms | 30 KΩ ≤ RL ≤ 1 MΩ, TJ = 25°C | 5 | ||
| Gain Bandwidth Product | 1 | 2 | MHz | Gv = 0 dB, TJ = 25°C | 5 | ||
| Input Threshold (Zero Duty-cycle) | 0.7 | 0.9 | V | Zero Duty-cycle | 5 | ||
| Input Threshold (Maximum Duty-cycle) | 3.3 | 3.6 | V | Maximum Duty-cycle | 5 | ||
| Maximum Duty-cycle | 45 | 49 | % | Note 2 | 5 | ||
| Soft Start Low Level | 0.4 | 0.7 | V | VSD = 2.5 V | 5 | ||
| Shutdown Threshold | 0.6 | 0.8 | 1 | V | To outputs, VSS = 5.1 V, TJ = 25°C | 5 | |
| Shutdown Input Current | 0.4 | 1 | mA | VSD = 2.5 V | 5 | ||
| Soft Start Current | 25 | 50 | 80 | µA | VSD = 0 V, VSS = 0 V | 5 | |
| Output Low Level (ISINK = 20 mA) | 0.2 | 0.4 | V | VC = 20 V; ISINK = 20 mA | 6 | ||
| Output Low Level (ISINK = 100 mA) | 1 | 2 | V | VC = 20 V; ISINK = 100 mA | 6 | ||
| Output High Level (ISOURCE = 20 mA) | 18 | 19 | V | VC = 20 V; ISOURCE = 20 mA | 6 | ||
| Output High Level (ISOURCE = 100 mA) | 17 | 18 | V | VC = 20 V; ISOURCE = 100 mA | 6 | ||
| Under-Voltage Lockout | 6 | 7 | 8 | V | VCOMP and VSS = High | 6 | |
| Rise Time | tR | 100 | 600 | ns | CL = 1 nF, TJ = 25°C | 6 | |
| Fall Time | tF | 50 | 300 | ns | CL = 1 nF, TJ = 25°C | 6 | |
| Supply Current | IS | 14 | 20 | mA | VIN = 35 V | 6 | |
| Maximum Frequency | fMAX | 400 | KHz | RT = 2 KΩ, CT = 0.001 μF | 5 | ||
| Minimum Frequency | fMIN | 100 | Hz | RT = 150 KΩ, CT = 0.1 μF | 5 | ||
| Thermal Resistance Junction-ambient (DIP16) | θJA | 80 | °C/W | DIP16 package | 4 |
CAD (KiCad official)
- Symbol:
U3525L-D16-T - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files:
u3525l-d16-t-etched.step/u3525l-d16-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);u3525l-d16-t.step/u3525l-d16-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: UTC(Unisonic Tech) datasheet (10 pp, sha256
e889eb2537c2a6f5, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# U3525L-D16-T
**UTC(Unisonic Tech)** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DIP-16
U3525L-D16-T from UTC(Unisonic Tech), in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | INV. INPUT | input | Inverting input of the error amplifier, with input bias current of 1 µA typ and 10 µA max and common-mode range of 1.5 to 5.2 V. |
| 2 | N.I. INPUT | input | Non-inverting input of the error amplifier, with input bias current of 1 µA typ and 10 µA max and common-mode range of 1.5 to 5.2 V. |
| 3 | SYNC | input | Separate oscillator sync terminal with a sync threshold of 1.2 to 2.8 V (2 V typ) and sync input current of 1 to 2.5 mA at 3.5 V. |
| 4 | OSC. OUTPUT | output | Oscillator clock output with a clock amplitude of 3 to 3.5 V and a clock width of 0.3 to 1 µs. |
| 5 | CT | passive | Oscillator timing capacitor connection with a recommended range of 0.001 to 0.1 µF. |
| 6 | RT | passive | Oscillator timing resistor connection with a recommended range of 2 to 150 kΩ. |
| 7 | DISCHARGE | passive | Oscillator discharge terminal where a dead time resistor (0 to 500 Ω) to CT sets the dead time. |
| 8 | SOFT-START | passive | Soft-start capacitor connection with a current-source pull-up of 25 to 80 µA, and pulling it down turns off the outputs. |
| 9 | COMP | bidirectional | Error amplifier output/compensation terminal with a current-source pull-up, and pulling it down (about 100 µA) turns off the outputs. |
| 10 | SHUT DOWN | input | Shutdown input with a threshold of 0.6 to 1 V that sets the PWM latch and discharges the soft-start capacitor with a 150 µA sink, and it should not be left floating. |
| 11 | OUTPUT A | output | Totem-pole output A that sources or sinks over 200 mA (500 mA absolute max) and gives a LOW output when off. |
| 12 | GROUND | power_in | Ground reference for the device. |
| 13 | VC | power_in | Collector supply for the output stages, with a recommended range of 4.5 to 35 V and an absolute maximum of 40 V. |
| 14 | OUTPUT B | output | Totem-pole output B that sources or sinks over 200 mA (500 mA absolute max) and gives a LOW output when off. |
| 15 | +VI | power_in | Input supply voltage with a recommended range of 8 to 35 V and an absolute maximum of 40 V. |
| 16 | VREF | power_out | Trimmed 5.1 V reference output (±1%) that supplies up to 20 mA of load current. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UTC(Unisonic Tech) |
| Package | DIP-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | ViN | | | 40 | V | | 4 |
| Collector Supply Voltage | VC | | | 40 | V | | 4 |
| Oscillator Charging Current | IOSC | | | 5 | mA | | 4 |
| Output Current, Source or Sink | Io | | | 500 | mA | | 4 |
| Reference Output Current | IR | | | 50 | mA | | 4 |
| Current through CT Terminal | IT | | | 5 | mA | | 4 |
| Logic Inputs voltage | | -0.3 | | 5.5 | V | | 4 |
| Total Power Dissipation | PD | | | 1000 | mW | Ta = 70 °C | 4 |
| Junction Temperature | TJ | -55 | | 125 | °C | | 4 |
| Operating Ambient Temperature | TORP | 0 | | 70 | °C | | 4 |
| Input Voltage | VIN | 8 | | 35 | V | | 4 |
| Collector Supply Voltage | VC | 4.5 | | 35 | V | | 4 |
| Sink/Source Load Current (steady state) | ISTEAD | 0 | | 100 | mA | | 4 |
| Sink/Source Load Current (peak) | IPEAK | 0 | | 400 | mA | | 4 |
| Reference Load Current | ILOAD | 0 | | 20 | mA | | 4 |
| Oscillator Frequency Range | FO | 100 | | 400 | KHz | | 4 |
| Oscillator Timing Resistor | RO | 2 | | 150 | KΩ | | 4 |
| Oscillator Timing Capacitor | CO | 0.001 | | 0.1 | μF | | 4 |
| Dead Time Resistor Range | RT | 0 | | 500 | Ω | | 4 |
| Output Voltage | VREF | 5 | 5.1 | 5.2 | V | TJ = 25°C | 5 |
| Total Output Variation | | 4.95 | | 5.25 | V | Line, Load and Temperature | 5 |
| Line Regulation | △VREF | | 10 | 20 | mV | VIN = 8 ~ 35 V | 5 |
| Load Regulation | △VREF | | 20 | 50 | mV | IL = 0 ~ 20 mA | 5 |
| Temp. Stability | △VREF/△T | | 20 | 50 | mV | Over Operating Range | 5 |
| Short Circuit Current | | | 80 | 100 | mA | VREF = 0, TJ = 25°C | 5 |
| Clock Amplitude | | | 3 | 3.5 | V | | 5 |
| Sync Threshold | | 1.2 | 2 | 2.8 | V | | 5 |
| Sync Input Current | | | 1 | 2.5 | mA | Sync Voltage = 3.5 V | 5 |
| Current Mirror | | 1.7 | 2 | 2.2 | mA | IRT = 2 mA | 5 |
| Clock Width | | 0.3 | 0.5 | 1 | μs | TJ = 25°C | 5 |
| Initial Accuracy | | -6 | 2 | 6 | % | TJ = 25°C | 5 |
| Voltage Stability | | -2 | 1 | 2 | % | VIN = 8 ~ 35 V | 5 |
| Temperature Stability | △f/△T | -6 | 3 | 6 | % | Over Operating Range | 5 |
| Output Low Level | | | 0.2 | 0.5 | V | VCM = 5.1 V | 5 |
| Output High Level | | | 3.8 | 5.6 | V | VCM = 5.1 V | 5 |
| Input Offset Voltage | VOS | | 2 | 10 | mV | VCM = 5.1 V | 5 |
| Input Bias Current | Ib | | 1 | 10 | μA | VCM = 5.1 V | 5 |
| Comm. Mode Reject. | CMR | | 60 | 75 | dB | VCM = 1.5 ~ 5.2 V | 5 |
| Supply Voltage Rejection | PSR | | 50 | 60 | dB | VIN = 8 ~ 35 V | 5 |
| DC Open Loop Gain | | | 60 | 75 | dB | RL ≥ 10 MΩ | 5 |
| DC Transconduct. | | | 1.1 | 1.5 | ms | 30 KΩ ≤ RL ≤ 1 MΩ, TJ = 25°C | 5 |
| Gain Bandwidth Product | | | 1 | 2 | MHz | Gv = 0 dB, TJ = 25°C | 5 |
| Input Threshold (Zero Duty-cycle) | | | 0.7 | 0.9 | V | Zero Duty-cycle | 5 |
| Input Threshold (Maximum Duty-cycle) | | | 3.3 | 3.6 | V | Maximum Duty-cycle | 5 |
| Maximum Duty-cycle | | | 45 | 49 | % | Note 2 | 5 |
| Soft Start Low Level | | | 0.4 | 0.7 | V | VSD = 2.5 V | 5 |
| Shutdown Threshold | | 0.6 | 0.8 | 1 | V | To outputs, VSS = 5.1 V, TJ = 25°C | 5 |
| Shutdown Input Current | | | 0.4 | 1 | mA | VSD = 2.5 V | 5 |
| Soft Start Current | | 25 | 50 | 80 | µA | VSD = 0 V, VSS = 0 V | 5 |
| Output Low Level (ISINK = 20 mA) | | | 0.2 | 0.4 | V | VC = 20 V; ISINK = 20 mA | 6 |
| Output Low Level (ISINK = 100 mA) | | | 1 | 2 | V | VC = 20 V; ISINK = 100 mA | 6 |
| Output High Level (ISOURCE = 20 mA) | | | 18 | 19 | V | VC = 20 V; ISOURCE = 20 mA | 6 |
| Output High Level (ISOURCE = 100 mA) | | | 17 | 18 | V | VC = 20 V; ISOURCE = 100 mA | 6 |
| Under-Voltage Lockout | | 6 | 7 | 8 | V | VCOMP and VSS = High | 6 |
| Rise Time | tR | | 100 | 600 | ns | CL = 1 nF, TJ = 25°C | 6 |
| Fall Time | tF | | 50 | 300 | ns | CL = 1 nF, TJ = 25°C | 6 |
| Supply Current | IS | | 14 | 20 | mA | VIN = 35 V | 6 |
| Maximum Frequency | fMAX | | 400 | | KHz | RT = 2 KΩ, CT = 0.001 μF | 5 |
| Minimum Frequency | fMIN | | 100 | | Hz | RT = 150 KΩ, CT = 0.1 μF | 5 |
| Thermal Resistance Junction-ambient (DIP16) | θJA | | 80 | | °C/W | DIP16 package | 4 |
## CAD (KiCad official)
- Symbol: `U3525L-D16-T`
- Footprint: `Package_DIP:DIP-16_W7.62mm`
- 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files: `u3525l-d16-t-etched.step` / `u3525l-d16-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `u3525l-d16-t.step` / `u3525l-d16-t.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [UTC(Unisonic Tech) datasheet](docs/u3525l-d16-t-datasheet.pdf) (10 pp, sha256 `e889eb2537c2a6f5`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/u3525l-d16-t-datasheet.pdf)