# U2115D

**UNI SEMIC** · Gate Drivers · SOP-8

U2115D from UNI SEMIC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Low side and logic fixed supply; recommended operating range is 5 V to 20 V, with an absolute maximum of -0.3 V to 25 V. |
| 2 | HIN | input | High side driver logic input, active high; input voltage must stay between 0 and VCC and is compatible with 3.3 V, 5 V and 15 V logic. |
| 3 | LIN | input | Low side driver logic input, active high for the U2115D; input voltage must stay between 0 and VCC. |
| 4 | COM | power_in | Low side return; all voltage parameters in the datasheet are referenced to COM. |
| 5 | LO | output | Low side gate drive output; VLO must stay between 0 V and VCC, with typical peak output current of 1.0 A source and 1.2 A sink. |
| 6 | VS | power_in | High side floating supply return (offset voltage); recommended range is -6 V to 200 V, with the logic operational over -6 V to 200 V. |
| 7 | HO | output | High side gate drive output; VHO must stay between VS and VB, with typical peak output current of 1.0 A source and 1.2 A sink. |
| 8 | VB | power_in | High side floating supply; recommended range is VS + 5 V to VS + 20 V, with an absolute maximum of -0.3 V to 225 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | UNI SEMIC |
| Package | SOP-8 |
| Category | Motor Driver ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High side floating absolute voltage | VB | -0.3 |  | 225 | V |  | 5 |
| Low side and logic fixed supply voltage | Vcc | -0.3 |  | 25 | V |  | 5 |
| Allowable offset supply voltage transient | dVS/dt |  |  | 55 | V/ns |  | 5 |
| Package power dissipation | PD |  |  | 0.625 | W | TA≤+25°C, SOIC-8 | 5 |
| Thermal resistance, junction to ambient | RthJA |  |  | 200 | °C/W | SOIC-8, board mounted, still air | 5 |
| Junction temperature | TJ | -35 |  | 150 | °C |  | 5 |
| Storage temperature | TS | -55 |  | 150 | °C |  | 5 |
| Lead temperature (soldering, 10 seconds) | TL |  |  | 300 | °C | soldering, 10 seconds | 5 |
| High side floating supply offset voltage | VS | -6 |  | 200 | V |  | 5 |
| Low side output voltage | VLO | 0 |  |  | V |  | 5 |
| Low side and logic fixed supply voltage | VCC | 5 |  | 20 | V |  | 5 |
| Logic input voltage (HIN & LIN) | VIN | 0 |  |  | V |  | 5 |
| Ambient temperature | TA | -40 |  | 150 | °C |  | 5 |
| Turn-on propagation delay | ton |  | 450 | 550 | ns | VS = 0V | 6 |
| Turn-off propagation delay | toff |  | 150 | 250 | ns | VS = 90V | 6 |
| Turn-on rise time | tr |  | 50 | 75 | ns |  | 6 |
| Turn-off fall time | tf |  | 25 | 50 | ns |  | 6 |
| Deadtime, LS turn-off to HS turn-on & HS turn-on to LS turn-off | DT | 240 | 300 | 360 | ns |  | 6 |
| Delay matching, HS & LS turn-on/off | MT |  |  | 60 | ns |  | 6 |
| VCC supply under-voltage positive going threshold | VCCUV+ |  | 4.5 | 5.5 | V |  | 6 |
| VCC supply under-voltage negative going threshold | VCCUV- |  | 4.1 | 5 | V |  | 6 |
| High side VBS supply under-voltage positive going threshold | VBSUV+ |  | 4.95 | 5.55 | V |  | 6 |
| High side VBS supply under-voltage negative going threshold | VBSUV- |  | 4.9 | 5.5 | V |  | 6 |
| Offset supply leakage current | ILK |  |  | 30 | uA | VB =VS =90V | 6 |
| Logic “1” (HO) & Logic “0” (LO) input voltage | VIH | 2.5 |  |  | V | VCC=5V to 20V | 6 |
| Logic “0” input bias current | IIN- |  |  | 1 | uA | VIN=5V LIN= 0V | 6 |
| High level output voltage, VBIAS - VO | VOH |  |  | 100 | mV | Io = 0A | 6 |
| Low level output voltage, VO | VOL |  |  | 100 | mV | Io =0A | 6 |
| Average forward current | IF(AV) |  |  | 0.8 | A |  | 7 |
| Under-voltage lockout hysteresis (VCC) | VCCHYS |  | 0.3 |  | V |  | 6 |
| High side VBS supply under-voltage lockout hysteresis | VBSUVHS |  | 0.1 |  | V |  | 6 |
| Quiescent VCC supply current | IQCC |  | 70 |  | uA | VIN =0V or 5V | 6 |
| Quiescent VBS supply current | IQBS |  | 20 |  | uA | VIN =0V or 5V | 6 |
| Logic “0” (HO) & Logic “1” (LO) input voltage | VIL |  | 1.6 |  | V | VCC=5V to 20V | 6 |
| Logic “1” input bias current | IIN+ |  | 10 |  | uA | VIN=5V LIN= 0V | 6 |
| Peak output source current (IO+) | IO+ |  | 1000 |  | mA | IF =0.5 A; VO= 0V, VIN = VIH; PW ≤10 us | 6 |
| Peak output sink current (IO-) | IO- |  | 1200 |  | mA | IF =0.5 A; VO= 0V, VIN = VIH; PW ≤10 us | 6 |
| Reverse breakdown voltage | VBR |  | 200 |  | V | IR = 0.1mA | 7 |
| Maximum forward voltage drop | VF |  | 1.2 |  | V | IF =0.5 A | 7 |

## CAD (KiCad official)

- Symbol: `U2115D`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `u2115d-etched.step` / `u2115d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `u2115d.step` / `u2115d.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [UNI SEMIC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8604434057417936896) (12 pp, sha256 `41d7bec578bb96fe`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/u2115d-datasheet.pdf)