# TX4130L

**XDS** · DC-DC Converters · SOP-8-EP

TX4130L from XDS, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | MOS transistor drain input, connected to the power supply input (VIN range 8-90V). |
| 2 | VDD | power_in | Chip supply input (VDD clamp voltage 33V typical, undervoltage turn-on 6V rising). |
| 3 | FB1 | input | Positive input of the output sampling feedback. |
| 4 | FB2 | input | Negative input of the output sampling feedback. |
| 5 | LDO | passive | Internal LDO filter pin (LDO voltage 5.5V). |
| 6 | VSS | power_in | Chip ground, also connected externally to the output inductor. |
| 7 | VSEN | input | Current sense input (VSEN voltage drop 150mV typical). |
| 8 | VSEND | passive | Source of the internal MOS transistor. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | XDS |
| Package | SOP-8-EP |
| Category | Power Management ICs |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| MOS drain input voltage | VIN | 8 |  | 90 | V |  | 4 |
| Feedback voltage difference VFB+ - VFB- | VBF | 369 | 380 | 391 | mV |  | 4 |
| VSEN voltage drop | VCS | 145 | 150 | 155 | mV |  | 4 |
| Startup current | Istart |  | 40 | 100 | μA | VDD 5V | 4 |
| VDD clamp voltage | VDD |  |  | 33 | V |  | 4 |
| Undervoltage protection on | VDD_ON |  | 6 |  | V | VDD rising | 4 |
| Undervoltage protection off | VDD_OFF |  | 4 |  | mV | VDD falling | 4 |
| Operating current | IOP |  | 1 |  | mA | DRV load | 4 |
| Overcurrent protection value | VCS_LMT |  | 300 |  | mV |  | 4 |
| Switching frequency | FS |  | 140 |  | kHz |  | 4 |
| MOS breakdown voltage | VDS |  | 100 |  | mΩ |  | 4 |
| MOS on-resistance | RDSON |  | 100 |  | mΩ | VGS=5V | 4 |
| Overtemperature protection threshold | OTP_TH |  | 150 |  | ℃ | temperature rising | 4 |
| Overtemperature protection hysteresis | OTP_HYS |  | 25 |  | ℃ |  | 4 |
| LDO VCC voltage | LDO |  | 5.5 |  | V |  | 4 |

## CAD (KiCad official)

- Symbol: `TX4130L`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files: `tx4130l-etched.step` / `tx4130l-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tx4130l.step` / `tx4130l.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [XDS datasheet](docs/tx4130l-datasheet.pdf) (6 pp, sha256 `71ed5e74fe480b10`, retrieved 2026-10-22, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tx4130l-datasheet.pdf)