TX4121

{
 "schema": "adom.pads/1",
 "slug": "tx4121",
 "footprint": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm",
 "generated_from": {
  "footprint": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm@sha256:5848244c5e72002e",
  "pins": "page.json:component.pins",
  "overrides": null
 },
 "pin1": {
  "pad": "1",
  "at": [
   -2.475,
   -1.905
  ],
  "corner": "top-left",
  "source": "silk-marker",
  "derived_from": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm@sha256:5848244c5e72002e"
 },
 "pad_count": 9,
 "symbol_pins": [
  "1",
  "2",
  "3",
  "4",
  "5",
  "6",
  "7",
  "8",
  "9"
 ],
 "paste_apertures": 4,
 "issues": [],
 "pads": [
  {
   "pad": "1",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.475,
    -1.905
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "1",
   "name": "BST",
   "type": "passive",
   "description": "Bootstrap driver pin for the high-side MOSFET gate drive. Connect a 0.1 µF (or larger) ceramic capacitor between BST and SW to develop the high-side gate drive rail.",
   "is_pin1": true,
   "source": {
    "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "2",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.475,
    -0.635
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "2",
   "name": "VDD",
   "type": "power_in",
   "description": "Chip power / converter input supply. Operating range 6.5V to 36V, absolute max 36V. Bypass locally to GND with low-ESR ceramic input capacitors.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "3",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.475,
    0.635
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "3",
   "name": "SW",
   "type": "power_out",
   "description": "Switching node output - drain junction of the internal high-side and low-side power MOSFETs. Connect to the external inductor. Delivers up to 3.1 A continuous.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "4",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.475,
    1.905
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "4",
   "name": "GND",
   "type": "power_in",
   "description": "Device ground / power return. Tie to the ground plane together with the EP thermal pad for best thermal and electrical performance.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "5",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.475,
    1.905
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "5",
   "name": "FB",
   "type": "input",
   "description": "Feedback sense input for the output voltage divider. Regulated to VFB = 0.9 V typical; output OVP threshold VFB_OVP = 0.99 V. Absolute max −0.3 V to 6 V.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "6",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.475,
    0.635
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "6",
   "name": "COMP",
   "type": "output",
   "description": "Error amplifier output / loop compensation node. Connect an R-C (and optional second C) network from COMP to GND to shape the control-loop response. Source ~5.2 µA, sink ~3.2 µA.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "7",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.475,
    -0.635
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "7",
   "name": "EN",
   "type": "input",
   "description": "Enable input, active-high, with an internal high-value pull-up (~1.6 µA input current). VIH ≥ 1.2 V, VIL ≤ 1.1 V. Absolute max −0.3 V to 6 V. Leave floating or tie high to enable; pull to GND to shut down.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "8",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.475,
    -1.905
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "8",
   "name": "SST",
   "type": "input",
   "description": "Programmable soft-start input. Connect a capacitor from SST to GND; the pin is charged by an internal ~2.3 µA source, ramping the internal reference to control output-voltage rise time and inrush current. Absolute max −0.3 V to 6 V.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "9",
   "kind": "smd",
   "shape": "rect",
   "at": [
    0.0,
    0.0
   ],
   "rot": 0.0,
   "size": [
    2.41,
    3.3
   ],
   "layers": [],
   "thermal": true,
   "pin": "9",
   "name": "EP",
   "type": "passive",
   "description": "Exposed thermal pad on the bottom of the ESOP-8 package. Solder to a large copper ground pour for heat sinking; electrically tie to GND (pin 4). θJA ≈ 56 °C/W, θJC ≈ 45 °C/W.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  }
 ]
}