# TX4121

**XDS** · DC-DC Converters · ESOP-8

TX4121 from XDS, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BST | passive | Bootstrap driver pin for the high-side MOSFET gate drive. Connect a 0.1 µF (or larger) ceramic capacitor between BST and SW to develop the high-side gate drive rail. |
| 2 | VDD | power_in | Chip power / converter input supply. Operating range 6.5V to 36V, absolute max 36V. Bypass locally to GND with low-ESR ceramic input capacitors. |
| 3 | SW | power_out | Switching node output - drain junction of the internal high-side and low-side power MOSFETs. Connect to the external inductor. Delivers up to 3.1 A continuous. |
| 4 | GND | power_in | Device ground / power return. Tie to the ground plane together with the EP thermal pad for best thermal and electrical performance. |
| 5 | FB | input | Feedback sense input for the output voltage divider. Regulated to VFB = 0.9 V typical; output OVP threshold VFB_OVP = 0.99 V. Absolute max −0.3 V to 6 V. |
| 6 | COMP | output | Error amplifier output / loop compensation node. Connect an R-C (and optional second C) network from COMP to GND to shape the control-loop response. Source ~5.2 µA, sink ~3.2 µA. |
| 7 | EN | input | Enable input, active-high, with an internal high-value pull-up (~1.6 µA input current). VIH ≥ 1.2 V, VIL ≤ 1.1 V. Absolute max −0.3 V to 6 V. Leave floating or tie high to enable; pull to GND to shut down. |
| 8 | SST | input | Programmable soft-start input. Connect a capacitor from SST to GND; the pin is charged by an internal ~2.3 µA source, ramping the internal reference to control output-voltage rise time and inrush current. Absolute max −0.3 V to 6 V. |
| 9 | EP | passive | Exposed thermal pad on the bottom of the ESOP-8 package. Solder to a large copper ground pour for heat sinking; electrically tie to GND (pin 4). θJA ≈ 56 °C/W, θJC ≈ 45 °C/W. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | XDS |
| Package | ESOP-8 |
| Category | PMIC |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| EN pin voltage | EN | -0.3 |  | 6 | V |  | 3 |
| SST pin voltage | SST | -0.3 |  | 6 | V |  | 3 |
| FB pin voltage | FB | -0.3 |  | 6 | V |  | 3 |
| Operating voltage (VDD) | VDD | 6.5 |  | 36 | V |  | 3 |
| Output current | IOUT | 0 |  | 3.1 | A |  | 3 |
| Operating junction temperature | JT | -40 |  | 125 | ℃ | 工作结温度 | 3 |
| Start-up minimum input voltage (UVLO rising) | VUVLO_up | 6.5 |  |  | V |  | 4 |
| EN high voltage | V_EN_H | 1.2 |  |  | V |  | 4 |
| EN low voltage | V_EN_L |  |  | 1.1 | V |  | 4 |
| High-side switch leakage current | I_leak_sw |  | 0 | 10 | uA | VEN = 0V, VSW= 0V | 4 |
| Shutdown voltage (UVLO falling) | VUVLO_down |  | 6 |  | V |  | 4 |
| UVLO hysteresis | VUVLO_hys |  | 0.5 |  | V |  | 4 |
| Quiescent current | IQ |  | 1 |  | mA | VFB=1.1V | 4 |
| Oscillator frequency | Fosc |  | 300 |  | KHz |  | 4 |
| Feedback voltage | VFB |  | 0.9 |  | V | 4.5≤VIN≤36V | 4 |
| Feedback overvoltage threshold | VFB_OVP |  | 0.99 |  | V |  | 4 |
| Maximum duty cycle | D_MAX |  | 94 |  | % | （注）由设计保证，未在生产中测试 | 4 |
| Minimum on-time | Ton |  | 100 |  | ns | （注）由设计保证，未在生产中测试 | 4 |
| High-side switch current limit | Hs_Iocl |  | 5.9 |  | A | 最小占空比 | 4 |
| Low-side switch current limit | Ls_Iocl |  | 5.5 |  | A |  | 4 |
| Input overvoltage protection threshold | Vinovp |  | 33 |  | V |  | 4 |
| Thermal shutdown temperature | TH_SD |  | 155 |  | ℃ | （注）由设计保证，未在生产中测试 | 4 |
| Thermal shutdown hysteresis | TH_sdhys |  | 15 |  | ℃ | （注）由设计保证，未在生产中测试 | 4 |
| High-side switch on-resistance | RDS(ON)_H |  | 79 |  | mΩ | IOUT = 1A，VOUT = 3.3V | 4 |
| Low-side switch on-resistance | RDS(ON)_L |  | 62 |  | mΩ | IOUT = 1A, VOUT = 3.3V | 4 |
| EN input current | I_EN_IN |  | 1.6 |  | uA |  | 4 |
| Soft-start charging current | I_SST_CHG |  | 2.3 |  | uA |  | 4 |
| Compensation source current | I_COMP_SRC |  | 5.2 |  | uA | VFB=1.0V | 4 |
| Compensation sink current | I_COMP_SNK |  | 3.2 |  | uA | VFB=0.8V | 4 |
| Junction-to-ambient thermal resistance (ESOP8) | θJA |  | 56 |  | ℃W |  | 3 |
| Junction-to-case thermal resistance (ESOP8) | θJC |  | 45 |  | ℃W |  | 3 |

## CAD (KiCad official)

- Symbol: `TX4121`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm`
- 3D model: ESOP-8 (KiCad packages3D, STEP)
- 3D model files: `tx4121-etched.step` / `tx4121-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tx4121.step` / `tx4121.glb` are the bare package body.

## 3D model downloads

Two STEP files. Same geometry, different body top:

| File | Size | Use it when |
|---|---|---|
| [`tx4121.step`](tx4121.step) | 193 KB | You want the bare part, or you mark your own boards. |
| [`tx4121-etched.step`](tx4121-etched.step) | 834 KB | You want the part with `TX4121` already on it. |

The marking in the etched file is real recessed geometry cut into the solid, not a
texture or a decal: 236 faces against 63 in the bare model. It
survives export, section views, and rendering in any CAD tool, and it drops straight
into KiCad or Fusion with no extra setup.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [XDS datasheet](docs/tx4121-datasheet.pdf) (12 pp, sha256 `d852293a9e759d95`, retrieved 2026-08-17, tier: lcsc)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tx4121-datasheet.pdf)