TVP5150AM1IPBSR from Texas Instruments, in a TQFP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AIP1A	input	Analog video input with a maximum input range of 0-0.75 VPP, to be coupled through a 0.1-µF capacitor and attenuated if the input amplitude is higher.
2	AIP1B	input	Analog video input with a maximum input range of 0-0.75 VPP, to be coupled through a 0.1-µF capacitor and attenuated if the input amplitude is higher.
3	PLL_AGND	power_in	PLL ground, to be connected to analog ground.
4	PLL_AVDD	power_in	PLL supply, to be connected to a 1.8-V analog supply.
5	XTAL1/OSC	input	External clock reference input.
6	XTAL2	output	External clock reference output, not connected when XTAL1 is driven by an external single-ended oscillator.
7	AGND	power_in	Substrate, to be connected to analog ground.
8	RESETB	input	Active-low reset that can be used only when PDN = 1; pulling it low resets all registers and restarts the internal microprocessor.
9	SCLK	output	System clock at 2x the frequency of the pixel clock.
10	IO_DVDD	power_in	Digital output supply, to be connected to a 3.3-V digital supply.
11	YOUT7/I2CSEL	bidirectional	YOUT7 is the MSB of the ITU-R BT.656 / YCbCr 4:2:2 output, and during reset it selects the I2C address (1 = BAh, 0 = B8h) and must be pulled high or low through a resistor greater than 1 kΩ.
12	YOUT6	output	Bit 6 of the ITU-R BT.656 / YCbCr 4:2:2 output with discrete syncs.
13	YOUT5	output	Bit 5 of the ITU-R BT.656 / YCbCr 4:2:2 output with discrete syncs.
14	YOUT4	output	Bit 4 of the ITU-R BT.656 / YCbCr 4:2:2 output with discrete syncs.
15	YOUT3	output	Bit 3 of the ITU-R BT.656 / YCbCr 4:2:2 output with discrete syncs.
16	YOUT2	output	Bit 2 of the ITU-R BT.656 / YCbCr 4:2:2 output with discrete syncs.
17	YOUT1	output	Bit 1 of the ITU-R BT.656 / YCbCr 4:2:2 output with discrete syncs.
18	YOUT0	output	Bit 0 (LSB) of the ITU-R BT.656 / YCbCr 4:2:2 output with discrete syncs.
19	DGND	power_in	Digital ground.
20	DVDD	power_in	Digital supply, to be connected to a 1.8-V digital supply.
21	SCL	bidirectional	I2C serial clock, open drain.
22	SDA	bidirectional	I2C serial data, open drain.
23	FID/GLCO	output	Field ID (1 indicates odd field) or vertical lock indicator, and GLCO serial color PLL output at the SCLK rate in Genlock mode or SCLK/4 in RTC mode.
24	VSYNC/PALI	output	Vertical synchronization signal, or PAL line indicator (1 = noninverted line, 0 = inverted line) or horizontal lock indicator depending on configuration.
25	HSYNC	output	Horizontal synchronization signal.
26	AVID	output	Active video indicator, high during the horizontal active time of the video AVID output, with toggling during vertical blanking controlled by register 12h bit 2.
27	INTREQ/GPCL/VBLK	output	Multiplexed output that is an interrupt request, a general-purpose control logic output, or a vertical blanking output as selected by I2C registers 03h and 0Fh; an external pullup or pulldown resistor is required under certain conditions.
28	PDN	input	Active-low power-down input that puts the decoder in standby mode while preserving register values.
29	REFP	output	ADC reference positive output, to be connected to analog ground through a 1-µF capacitor.
30	REFM	output	ADC reference negative output, to be connected to analog ground through a 1-µF capacitor and recommended to be connected directly to REFP through a 1-µF capacitor.
31	CH_AGND	power_in	Analog ground.
32	CH_AVDD	power_in	Analog supply, to be connected to a 1.8-V analog supply.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TQFP-32(5x5)
Category	Interface
Pins	32

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Industrial operating free-air temperature	TA	-40		85	°C	Industrial	74
Digital I/O supply voltage	IO_DVDD	3	3.3	3.6	V		74
Digital supply voltage	DVDD	1.65	1.8	1.95	V		74
Analog PLL supply voltage	PLL_AVDD	1.65	1.8	1.95	V		74
Analog core supply voltage	CH_AVDD	1.65	1.8	1.95	V		74
Analog input voltage (ac-coupling necessary)	VI(P-P)	0		0.75	V	ac-coupling necessary	74
Digital input voltage high	VIH	0.7			V	value is 0.7 × IO_DVDD as printed	74
Digital input voltage low	VIL			0.3	V	value is 0.3 × IO_DVDD as printed	74
XTAL input voltage high	VIH_XTAL	0.7			V	value is 0.7 × PLL_AVDD as printed	74
XTAL input voltage low	VIL_XTAL			0.3	V	value is 0.3 × PLL_AVDD as printed	74
High-level output current	IOH			2	mA		74
Low-level output current	IOL	-2			mA		74
SCLK high-level output current	IOH_SCLK			4	mA		74
SCLK low-level output current	IOL_SCLK	-4			mA		74
Frequency tolerance	Δf	-50		50	ppm	Specified by design	74
Reference clock frequency	f		14.3182		MHz		74
Supply voltage range IO_DVDD to DGND	IO_DVDD	-0.5		4.5	V	over operating free-air temperature range	74
Supply voltage range DVDD to DGND	DVDD	-0.5		2.3	V	over operating free-air temperature range	74
Supply voltage range PLL_AVDD to PLL_AGND	PLL_AVDD	-0.5		2.3	V	over operating free-air temperature range	74
Supply voltage range CH_AVDD to CH_AGND	CH_AVDD	-0.5		2.3	V	over operating free-air temperature range	74
Digital input voltage range to DGND	VI	-0.5		4.5	V	over operating free-air temperature range	74
Input voltage range XTAL1 to PLL_GND	XTAL1	-0.5		2.3	V	over operating free-air temperature range	74
Analog input voltage range to CH_AGND	AI	-0.2		2	V	over operating free-air temperature range	74
Digital output voltage range to DGND	VO	-0.5		4.5	V	over operating free-air temperature range	74
Industrial operating free-air temperature	TA	-40		85	°C	Industrial	74
Storage temperature range	Tstg	-65		150	°C		74
Input current high	IIH	-20		20	µA	VI = VIH	75
Input current low	IIL	-20		20	µA	VI = VIL	75
3.3-V I/O digital supply current	IDD(IO_D)		4.8	6.2	mA	Color bar input	75
1.8-V digital supply current	IDD(D)		25.3	32.9	mA	Color bar input	75
1.8-V analog PLL supply current	IDD(PLL_A)		5.4	7.1	mA	Color bar input	75
1.8-V analog core supply current	IDD(CH_A)		24.4	31.7	mA	Color bar input	75
Total power dissipation, normal mode	PTOT		115	150	mW	Color bar input	75
Total power dissipation, power-down mode	PDOWN			1	mW	Color bar input	75
Input capacitance	Ci		8		pF	By design	75
Output voltage high	VOH	0.8			V	IOH = 2 mA; value is 0.8 × IO_DVDD as printed	75
Output voltage low	VOL			0.22	V	IOL = -2 mA; value is 0.22 × IO_DVDD as printed	75
SCLK output voltage high	VOH_SCLK	0.8			V	IOH = 4 mA; value is 0.8 × IO_DVDD as printed	75
SCLK output voltage low	VOL_SCLK			0.22	V	IOL = -4 mA; value is 0.22 × IO_DVDD as printed	75
Input impedance, analog video inputs	Zi		500		kΩ	By design	75
Input capacitance, analog video inputs	Ci		10		pF	By design	75
Input voltage range	Vi(pp)	0		0.75	V	Ccoupling = 0.1 µF	75
Gain control maximum	ΔG			12	dB		75
Gain control minimum	ΔG	0			dB		75
DC differential nonlinearity	DNL	-1	0.5	1	LSB	ADC only	75
DC integral nonlinearity	INL	-2.5	1	2.5	LSB	ADC only	75
Frequency response	Fr	-3		-0.9	dB	6 MHz, specified by design	75
Signal-to-noise ratio	SNR	50			dB	6 MHz, 1.0 VP-P	75
Noise spectrum	NS	50			dB	50% flat field	75
Differential phase	DP			1.5	°		75
Differential gain	DG			0.5	%		75
SCLK high time	t1	13.4	14.5	16.4	ns	≥90%	76
SCLK low time	t2	13.4	14.5	16.4	ns	≤10%	76
SCLK fall time	t3	2	4	5	ns	90% to 10%	76
SCLK rise time	t4	2	4	5	ns	10% to 90%	76
Output hold time	t5	2			ns		76
Output delay time	t6	3		8	ns		76
Duty cycle, SCLK			50		%		76

CAD (KiCad official)

Symbol: TVP5150AM1IPBSR
Footprint: Package_QFP:TQFP-32_5x5mm_P0.5mm
3D model: TQFP-32(5x5) (KiCad packages3D, STEP)
3D model files: tvp5150am1ipbsr-etched.step / tvp5150am1ipbsr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tvp5150am1ipbsr.step / tvp5150am1ipbsr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (87 pp, sha256 0d57650c898dc79c, retrieved 2026-11-06, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

TVP5150AM1IPBSR

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3D Model

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