component
TUSB8044ARGCR
Public Made by Adomby adom
Texas Instruments USB Converters, VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TUSB8044ARGCR
Texas Instruments · USB Converters · VQFN-64-EP(9x9)
TUSB8044ARGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | USB_DP_DN1 | bidirectional | USB high-speed differential transceiver (positive) for downstream port 1. |
| 2 | USB_DM_DN1 | bidirectional | USB high-speed differential transceiver (negative) for downstream port 1. |
| 3 | USB_SSTXP_DN1 | output | USB SuperSpeed transmitter differential pair (positive) for downstream port 1. |
| 4 | USB_SSTXM_DN1 | output | USB SuperSpeed transmitter differential pair (negative) for downstream port 1. |
| 5 | VDD | power_in | 1.1-V power rail; recommended 0.99 V to 1.26 V, absolute maximum 1.4 V. |
| 6 | USB_SSRXP_DN1 | input | USB SuperSpeed receiver differential pair (positive) for downstream port 1. |
| 7 | USB_SSRXM_DN1 | input | USB SuperSpeed receiver differential pair (negative) for downstream port 1. |
| 8 | VDD | power_in | 1.1-V power rail; recommended 0.99 V to 1.26 V, absolute maximum 1.4 V. |
| 9 | USB_DP_DN2 | bidirectional | USB high-speed differential transceiver (positive) for downstream port 2. |
| 10 | USB_DM_DN2 | bidirectional | USB high-speed differential transceiver (negative) for downstream port 2. |
| 11 | USB_SSTXP_DN2 | output | USB SuperSpeed transmitter differential pair (positive) for downstream port 2. |
| 12 | USB_SSTXM_DN2 | output | USB SuperSpeed transmitter differential pair (negative) for downstream port 2. |
| 13 | VDD | power_in | 1.1-V power rail; recommended 0.99 V to 1.26 V, absolute maximum 1.4 V. |
| 14 | USB_SSRXP_DN2 | input | USB SuperSpeed receiver differential pair (positive) for downstream port 2. |
| 15 | USB_SSRXM_DN2 | input | USB SuperSpeed receiver differential pair (negative) for downstream port 2. |
| 16 | VDD33 | power_in | 3.3-V power rail; recommended 3.0 V to 3.6 V, absolute maximum 3.8 V. |
| 17 | USB_DP_DN3 | bidirectional | USB high-speed differential transceiver (positive) for downstream port 3. |
| 18 | USB_DM_DN3 | bidirectional | USB high-speed differential transceiver (negative) for downstream port 3. |
| 19 | USB_SSTXP_DN3 | output | USB SuperSpeed transmitter differential pair (positive) for downstream port 3. |
| 20 | USB_SSTXM_DN3 | output | USB SuperSpeed transmitter differential pair (negative) for downstream port 3. |
| 21 | VDD | power_in | 1.1-V power rail; recommended 0.99 V to 1.26 V, absolute maximum 1.4 V. |
| 22 | USB_SSRXP_DN3 | input | USB SuperSpeed receiver differential pair (positive) for downstream port 3. |
| 23 | USB_SSRXM_DN3 | input | USB SuperSpeed receiver differential pair (negative) for downstream port 3. |
| 24 | USB_DP_DN4 | bidirectional | USB high-speed differential transceiver (positive) for downstream port 4. |
| 25 | USB_DM_DN4 | bidirectional | USB high-speed differential transceiver (negative) for downstream port 4. |
| 26 | USB_SSTXP_DN4 | output | USB SuperSpeed transmitter differential pair (positive) for downstream port 4. |
| 27 | USB_SSTXM_DN4 | output | USB SuperSpeed transmitter differential pair (negative) for downstream port 4. |
| 28 | VDD | power_in | 1.1-V power rail; recommended 0.99 V to 1.26 V, absolute maximum 1.4 V. |
| 29 | USB_SSRXP_DN4 | input | USB SuperSpeed receiver differential pair (positive) for downstream port 4. |
| 30 | USB_SSRXM_DN4 | input | USB SuperSpeed receiver differential pair (negative) for downstream port 4. |
| 31 | VDD | power_in | 1.1-V power rail; recommended 0.99 V to 1.26 V, absolute maximum 1.4 V. |
| 32 | PWRCTL4/BATEN4 | bidirectional | Port 4 power-on control for the downstream power switch and battery charging enable; the level sampled at reset de-assertion sets battery charging support (0 = not supported, 1 = supported), internal pull-down, may be left unconnected if power management is not implemented. |
| 33 | PWRCTL3/BATEN3 | bidirectional | Port 3 power-on control for the downstream power switch and battery charging enable; the level sampled at reset de-assertion sets battery charging support (0 = not supported, 1 = supported), internal pull-down, may be left unconnected if power management is not implemented. |
| 34 | VDD33 | power_in | 3.3-V power rail; recommended 3.0 V to 3.6 V, absolute maximum 3.8 V. |
| 35 | PWRCTL2/BATEN2 | bidirectional | Port 2 power-on control for the downstream power switch and battery charging enable; the level sampled at reset de-assertion sets battery charging support (0 = not supported, 1 = supported), internal pull-down, may be left unconnected if power management is not implemented. |
| 36 | PWRCTL1/BATEN1 | bidirectional | Port 1 power-on control for the downstream power switch and battery charging enable; the level sampled at reset de-assertion sets battery charging support (0 = not supported, 1 = supported), internal pull-down, may be left unconnected if power management is not implemented. |
| 37 | SDA/SMBDAT | bidirectional | I2C data (when SMBUSz = 1, serial data for an I2C EEPROM) or SMBus data (when SMBUSz = 0, for an SMBus host); internal pull-down, can be left unconnected if the external interface is not implemented. |
| 38 | SCL/SMBCLK | bidirectional | I2C clock (when SMBUSz = 1, serial clock for an I2C EEPROM) or SMBus clock (when SMBUSz = 0, for an SMBus host); internal pull-down, can be left unconnected if the external interface is not implemented. |
| 39 | SMBUSz,SS_SUSPEND | bidirectional | Sampled at reset de-assertion to select I2C mode (1) or SMBus mode (0); after reset, indicates SuperSpeed upstream suspend status (1 = suspended) when enabled through stsOutputEn; internal pull-up, can be left unconnected if the external interface is not implemented. |
| 40 | BBbmConfigured0/FULLAUTOz/FULLPWRMGMTz/SS_UP | bidirectional | In I2C mode, sets bmConfigured[0] of the Billboard Capability descriptor together with pin 45; in SMBus mode, sampled or used for FullAutoEn/power switch control, or as SS_UP upstream SuperSpeed connection indicator when stsOutputEn is set (1 = SuperSpeed upstream connected); internal pull-down. |
| 41 | PWRCTL_POL | bidirectional | Sampled at reset de-assertion to set the polarity of PWRCTL[4:1] (0 = active low, 1 = active high); internal pull-up. |
| 42 | BBEN/GANGED,HS_UP | bidirectional | In I2C mode, Billboard enable (high presents the billboard to the host); in SMBus mode, sampled at reset to select individual (0) or ganged (1) port power control, or as HS_UP upstream high-speed connection indicator when stsOutputEn is set; internal pull-down. |
| 43 | OVERCUR4z | input | Port 4 over-current detection input from the downstream power switch (0 = over-current has occurred, 1 = no over-current); internal pull-up, may be left unconnected when another OVERCURz pin is used in ganged mode. |
| 44 | OVERCUR3z | input | Port 3 over-current detection input from the downstream power switch (0 = over-current has occurred, 1 = no over-current); internal pull-up, may be left unconnected when another OVERCURz pin is used in ganged mode. |
| 45 | BBbmConfigured1/AUTOENz/HS_SUSPEND | bidirectional | In I2C mode, sets bmConfigured[1] of the Billboard Capability descriptor together with pin 40; in SMBus mode, sampled to set autoEnz in the Battery Charging Support register, or as HS_SUSPEND upstream high-speed suspend indicator when stsOutputEn is set (1 = suspended); internal pull-down. |
| 46 | OVERCUR1z | input | Port 1 over-current detection input from the downstream power switch (0 = over-current has occurred, 1 = no over-current); internal pull-up, may be left unconnected when another OVERCURz pin is used in ganged mode. |
| 47 | OVERCUR2z | input | Port 2 over-current detection input from the downstream power switch (0 = over-current has occurred, 1 = no over-current); internal pull-up, may be left unconnected when another OVERCURz pin is used in ganged mode. |
| 48 | USB_VBUS | input | Upstream port VBUS detection input, which requires a voltage divider: connect to VBUS through 90.9 kΩ ±1% and to ground through 10 kΩ ±1%; voltage range 0 to 1.155 V at this terminal. |
| 49 | TEST | input | Reserved for factory test; requires an external pull-down resistor to ground on the PCB (10 kΩ or stronger recommended) for normal operation. |
| 50 | GRSTz | input | Global power reset; asserting it returns all internal registers to default states and the device is completely nonfunctional while asserted; internal pull-up. |
| 51 | VDD | power_in | 1.1-V power rail; recommended 0.99 V to 1.26 V, absolute maximum 1.4 V. |
| 52 | VDD33 | power_in | 3.3-V power rail; recommended 3.0 V to 3.6 V, absolute maximum 3.8 V. |
| 53 | USB_DP_UP | bidirectional | USB high-speed differential transceiver (positive) for the upstream port. |
| 54 | USB_DM_UP | bidirectional | USB high-speed differential transceiver (negative) for the upstream port. |
| 55 | USB_SSTXP_UP | output | USB SuperSpeed transmitter differential pair (positive) for the upstream port. |
| 56 | USB_SSTXM_UP | output | USB SuperSpeed transmitter differential pair (negative) for the upstream port. |
| 57 | VDD | power_in | 1.1-V power rail; recommended 0.99 V to 1.26 V, absolute maximum 1.4 V. |
| 58 | USB_SSRXP_UP | input | USB SuperSpeed receiver differential pair (positive) for the upstream port. |
| 59 | USB_SSRXM_UP | input | USB SuperSpeed receiver differential pair (negative) for the upstream port. |
| 60 | NC | unconnected | No connect; leave floating. |
| 61 | XO | output | Crystal output of the internal oscillator; may be left unconnected if XI is driven by an external oscillator, and a 1-MΩ feedback resistor is required between XI and XO when using a crystal. |
| 62 | XI | input | Crystal input for the internal oscillator, which may alternately be driven by an external oscillator; a 1-MΩ feedback resistor is required between XI and XO when using a crystal. |
| 63 | VDD33 | power_in | 3.3-V power rail; recommended 3.0 V to 3.6 V, absolute maximum 3.8 V. |
| 64 | USB_R1 | input | Precision resistor reference; a 9.53 kΩ ±1% resistor should be connected between USB_R1 and GND. |
| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-64-EP(9x9) |
| Category | Interface |
| Pins | 65 |
CAD (KiCad official)
- Symbol:
TUSB8044ARGCR - Footprint:
Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm - 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
- 3D model files:
tusb8044argcr-etched.step/tusb8044argcr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tusb8044argcr.step/tusb8044argcr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (69 pp, sha256
57142228db173b28, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TUSB8044ARGCR
**Texas Instruments** · USB Converters · VQFN-64-EP(9x9)
TUSB8044ARGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | USB_DP_DN1 | bidirectional | USB high-speed differential transceiver (positive) for downstream port 1. |
| 2 | USB_DM_DN1 | bidirectional | USB high-speed differential transceiver (negative) for downstream port 1. |
| 3 | USB_SSTXP_DN1 | output | USB SuperSpeed transmitter differential pair (positive) for downstream port 1. |
| 4 | USB_SSTXM_DN1 | output | USB SuperSpeed transmitter differential pair (negative) for downstream port 1. |
| 5 | VDD | power_in | 1.1-V power rail; recommended 0.99 V to 1.26 V, absolute maximum 1.4 V. |
| 6 | USB_SSRXP_DN1 | input | USB SuperSpeed receiver differential pair (positive) for downstream port 1. |
| 7 | USB_SSRXM_DN1 | input | USB SuperSpeed receiver differential pair (negative) for downstream port 1. |
| 8 | VDD | power_in | 1.1-V power rail; recommended 0.99 V to 1.26 V, absolute maximum 1.4 V. |
| 9 | USB_DP_DN2 | bidirectional | USB high-speed differential transceiver (positive) for downstream port 2. |
| 10 | USB_DM_DN2 | bidirectional | USB high-speed differential transceiver (negative) for downstream port 2. |
| 11 | USB_SSTXP_DN2 | output | USB SuperSpeed transmitter differential pair (positive) for downstream port 2. |
| 12 | USB_SSTXM_DN2 | output | USB SuperSpeed transmitter differential pair (negative) for downstream port 2. |
| 13 | VDD | power_in | 1.1-V power rail; recommended 0.99 V to 1.26 V, absolute maximum 1.4 V. |
| 14 | USB_SSRXP_DN2 | input | USB SuperSpeed receiver differential pair (positive) for downstream port 2. |
| 15 | USB_SSRXM_DN2 | input | USB SuperSpeed receiver differential pair (negative) for downstream port 2. |
| 16 | VDD33 | power_in | 3.3-V power rail; recommended 3.0 V to 3.6 V, absolute maximum 3.8 V. |
| 17 | USB_DP_DN3 | bidirectional | USB high-speed differential transceiver (positive) for downstream port 3. |
| 18 | USB_DM_DN3 | bidirectional | USB high-speed differential transceiver (negative) for downstream port 3. |
| 19 | USB_SSTXP_DN3 | output | USB SuperSpeed transmitter differential pair (positive) for downstream port 3. |
| 20 | USB_SSTXM_DN3 | output | USB SuperSpeed transmitter differential pair (negative) for downstream port 3. |
| 21 | VDD | power_in | 1.1-V power rail; recommended 0.99 V to 1.26 V, absolute maximum 1.4 V. |
| 22 | USB_SSRXP_DN3 | input | USB SuperSpeed receiver differential pair (positive) for downstream port 3. |
| 23 | USB_SSRXM_DN3 | input | USB SuperSpeed receiver differential pair (negative) for downstream port 3. |
| 24 | USB_DP_DN4 | bidirectional | USB high-speed differential transceiver (positive) for downstream port 4. |
| 25 | USB_DM_DN4 | bidirectional | USB high-speed differential transceiver (negative) for downstream port 4. |
| 26 | USB_SSTXP_DN4 | output | USB SuperSpeed transmitter differential pair (positive) for downstream port 4. |
| 27 | USB_SSTXM_DN4 | output | USB SuperSpeed transmitter differential pair (negative) for downstream port 4. |
| 28 | VDD | power_in | 1.1-V power rail; recommended 0.99 V to 1.26 V, absolute maximum 1.4 V. |
| 29 | USB_SSRXP_DN4 | input | USB SuperSpeed receiver differential pair (positive) for downstream port 4. |
| 30 | USB_SSRXM_DN4 | input | USB SuperSpeed receiver differential pair (negative) for downstream port 4. |
| 31 | VDD | power_in | 1.1-V power rail; recommended 0.99 V to 1.26 V, absolute maximum 1.4 V. |
| 32 | PWRCTL4/BATEN4 | bidirectional | Port 4 power-on control for the downstream power switch and battery charging enable; the level sampled at reset de-assertion sets battery charging support (0 = not supported, 1 = supported), internal pull-down, may be left unconnected if power management is not implemented. |
| 33 | PWRCTL3/BATEN3 | bidirectional | Port 3 power-on control for the downstream power switch and battery charging enable; the level sampled at reset de-assertion sets battery charging support (0 = not supported, 1 = supported), internal pull-down, may be left unconnected if power management is not implemented. |
| 34 | VDD33 | power_in | 3.3-V power rail; recommended 3.0 V to 3.6 V, absolute maximum 3.8 V. |
| 35 | PWRCTL2/BATEN2 | bidirectional | Port 2 power-on control for the downstream power switch and battery charging enable; the level sampled at reset de-assertion sets battery charging support (0 = not supported, 1 = supported), internal pull-down, may be left unconnected if power management is not implemented. |
| 36 | PWRCTL1/BATEN1 | bidirectional | Port 1 power-on control for the downstream power switch and battery charging enable; the level sampled at reset de-assertion sets battery charging support (0 = not supported, 1 = supported), internal pull-down, may be left unconnected if power management is not implemented. |
| 37 | SDA/SMBDAT | bidirectional | I2C data (when SMBUSz = 1, serial data for an I2C EEPROM) or SMBus data (when SMBUSz = 0, for an SMBus host); internal pull-down, can be left unconnected if the external interface is not implemented. |
| 38 | SCL/SMBCLK | bidirectional | I2C clock (when SMBUSz = 1, serial clock for an I2C EEPROM) or SMBus clock (when SMBUSz = 0, for an SMBus host); internal pull-down, can be left unconnected if the external interface is not implemented. |
| 39 | SMBUSz,SS_SUSPEND | bidirectional | Sampled at reset de-assertion to select I2C mode (1) or SMBus mode (0); after reset, indicates SuperSpeed upstream suspend status (1 = suspended) when enabled through stsOutputEn; internal pull-up, can be left unconnected if the external interface is not implemented. |
| 40 | BBbmConfigured0/FULLAUTOz/FULLPWRMGMTz/SS_UP | bidirectional | In I2C mode, sets bmConfigured[0] of the Billboard Capability descriptor together with pin 45; in SMBus mode, sampled or used for FullAutoEn/power switch control, or as SS_UP upstream SuperSpeed connection indicator when stsOutputEn is set (1 = SuperSpeed upstream connected); internal pull-down. |
| 41 | PWRCTL_POL | bidirectional | Sampled at reset de-assertion to set the polarity of PWRCTL[4:1] (0 = active low, 1 = active high); internal pull-up. |
| 42 | BBEN/GANGED,HS_UP | bidirectional | In I2C mode, Billboard enable (high presents the billboard to the host); in SMBus mode, sampled at reset to select individual (0) or ganged (1) port power control, or as HS_UP upstream high-speed connection indicator when stsOutputEn is set; internal pull-down. |
| 43 | OVERCUR4z | input | Port 4 over-current detection input from the downstream power switch (0 = over-current has occurred, 1 = no over-current); internal pull-up, may be left unconnected when another OVERCURz pin is used in ganged mode. |
| 44 | OVERCUR3z | input | Port 3 over-current detection input from the downstream power switch (0 = over-current has occurred, 1 = no over-current); internal pull-up, may be left unconnected when another OVERCURz pin is used in ganged mode. |
| 45 | BBbmConfigured1/AUTOENz/HS_SUSPEND | bidirectional | In I2C mode, sets bmConfigured[1] of the Billboard Capability descriptor together with pin 40; in SMBus mode, sampled to set autoEnz in the Battery Charging Support register, or as HS_SUSPEND upstream high-speed suspend indicator when stsOutputEn is set (1 = suspended); internal pull-down. |
| 46 | OVERCUR1z | input | Port 1 over-current detection input from the downstream power switch (0 = over-current has occurred, 1 = no over-current); internal pull-up, may be left unconnected when another OVERCURz pin is used in ganged mode. |
| 47 | OVERCUR2z | input | Port 2 over-current detection input from the downstream power switch (0 = over-current has occurred, 1 = no over-current); internal pull-up, may be left unconnected when another OVERCURz pin is used in ganged mode. |
| 48 | USB_VBUS | input | Upstream port VBUS detection input, which requires a voltage divider: connect to VBUS through 90.9 kΩ ±1% and to ground through 10 kΩ ±1%; voltage range 0 to 1.155 V at this terminal. |
| 49 | TEST | input | Reserved for factory test; requires an external pull-down resistor to ground on the PCB (10 kΩ or stronger recommended) for normal operation. |
| 50 | GRSTz | input | Global power reset; asserting it returns all internal registers to default states and the device is completely nonfunctional while asserted; internal pull-up. |
| 51 | VDD | power_in | 1.1-V power rail; recommended 0.99 V to 1.26 V, absolute maximum 1.4 V. |
| 52 | VDD33 | power_in | 3.3-V power rail; recommended 3.0 V to 3.6 V, absolute maximum 3.8 V. |
| 53 | USB_DP_UP | bidirectional | USB high-speed differential transceiver (positive) for the upstream port. |
| 54 | USB_DM_UP | bidirectional | USB high-speed differential transceiver (negative) for the upstream port. |
| 55 | USB_SSTXP_UP | output | USB SuperSpeed transmitter differential pair (positive) for the upstream port. |
| 56 | USB_SSTXM_UP | output | USB SuperSpeed transmitter differential pair (negative) for the upstream port. |
| 57 | VDD | power_in | 1.1-V power rail; recommended 0.99 V to 1.26 V, absolute maximum 1.4 V. |
| 58 | USB_SSRXP_UP | input | USB SuperSpeed receiver differential pair (positive) for the upstream port. |
| 59 | USB_SSRXM_UP | input | USB SuperSpeed receiver differential pair (negative) for the upstream port. |
| 60 | NC | unconnected | No connect; leave floating. |
| 61 | XO | output | Crystal output of the internal oscillator; may be left unconnected if XI is driven by an external oscillator, and a 1-MΩ feedback resistor is required between XI and XO when using a crystal. |
| 62 | XI | input | Crystal input for the internal oscillator, which may alternately be driven by an external oscillator; a 1-MΩ feedback resistor is required between XI and XO when using a crystal. |
| 63 | VDD33 | power_in | 3.3-V power rail; recommended 3.0 V to 3.6 V, absolute maximum 3.8 V. |
| 64 | USB_R1 | input | Precision resistor reference; a 9.53 kΩ ±1% resistor should be connected between USB_R1 and GND. |
| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-64-EP(9x9) |
| Category | Interface |
| Pins | 65 |
## CAD (KiCad official)
- Symbol: `TUSB8044ARGCR`
- Footprint: `Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm`
- 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
- 3D model files: `tusb8044argcr-etched.step` / `tusb8044argcr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tusb8044argcr.step` / `tusb8044argcr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tusb8044a) (69 pp, sha256 `57142228db173b28`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tusb8044argcr-datasheet.pdf)