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TUSB8044AIRGCR

Public Made by Adom

by adom

Texas Instruments USB ICs, VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232tusb8044airgcrfactory-2.0.0extractor-text
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TUSB8044AIRGCR

Texas Instruments · USB ICs · VQFN-64-EP(9x9)

TUSB8044AIRGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 USB_DP_DN1 bidirectional USB High-speed differential transceiver positive terminal for downstream port 1.
2 USB_DM_DN1 bidirectional USB High-speed differential transceiver negative terminal for downstream port 1.
3 USB_SSTXP_DN1 output USB SuperSpeed transmitter differential pair positive terminal for downstream port 1.
4 USB_SSTXM_DN1 output USB SuperSpeed transmitter differential pair negative terminal for downstream port 1.
5 VDD power_in 1.1-V power supply input voltage.
6 USB_SSRXP_DN1 input USB SuperSpeed receiver differential pair positive terminal for downstream port 1.
7 USB_SSRXM_DN1 input USB SuperSpeed receiver differential pair negative terminal for downstream port 1.
8 VDD power_in 1.1-V power supply input voltage.
9 USB_DP_DN2 bidirectional USB High-speed differential transceiver positive terminal for downstream port 2.
10 USB_DM_DN2 bidirectional USB High-speed differential transceiver negative terminal for downstream port 2.
11 USB_SSTXP_DN2 output USB SuperSpeed transmitter differential pair positive terminal for downstream port 2.
12 USB_SSTXM_DN2 output USB SuperSpeed transmitter differential pair negative terminal for downstream port 2.
13 VDD power_in 1.1-V power supply input voltage.
14 USB_SSRXP_DN2 input USB SuperSpeed receiver differential pair positive terminal for downstream port 2.
15 USB_SSRXM_DN2 input USB SuperSpeed receiver differential pair negative terminal for downstream port 2.
16 VDD33 power_in 3.3-V power supply input voltage.
17 USB_DP_DN3 bidirectional USB High-speed differential transceiver positive terminal for downstream port 3.
18 USB_DM_DN3 bidirectional USB High-speed differential transceiver negative terminal for downstream port 3.
19 USB_SSTXP_DN3 output USB SuperSpeed transmitter differential pair positive terminal for downstream port 3.
20 USB_SSTXM_DN3 output USB SuperSpeed transmitter differential pair negative terminal for downstream port 3.
21 VDD power_in 1.1-V power supply input voltage.
22 USB_SSRXP_DN3 input USB SuperSpeed receiver differential pair positive terminal for downstream port 3.
23 USB_SSRXM_DN3 input USB SuperSpeed receiver differential pair negative terminal for downstream port 3.
24 USB_DP_DN4 bidirectional USB High-speed differential transceiver positive terminal for downstream port 4.
25 USB_DM_DN4 bidirectional USB High-speed differential transceiver negative terminal for downstream port 4.
26 USB_SSTXP_DN4 output USB SuperSpeed transmitter differential pair positive terminal for downstream port 4.
27 USB_SSTXM_DN4 output USB SuperSpeed transmitter differential pair negative terminal for downstream port 4.
28 VDD power_in 1.1-V power supply input voltage.
29 USB_SSRXP_DN4 input USB SuperSpeed receiver differential pair positive terminal for downstream port 4.
30 USB_SSRXM_DN4 input USB SuperSpeed receiver differential pair negative terminal for downstream port 4.
31 VDD power_in 1.1-V power supply input voltage.
32 PWRCTL4/BATEN4 bidirectional Downstream port 4 power control output sampled at reset deassertion to indicate battery charging support (0 = not supported, 1 = supported).
33 PWRCTL3/BATEN3 bidirectional Downstream port 3 power control output sampled at reset deassertion to indicate battery charging support (0 = not supported, 1 = supported).
34 VDD33 power_in 3.3-V power supply input voltage.
35 PWRCTL2/BATEN2 bidirectional Downstream port 2 power control output sampled at reset deassertion to indicate battery charging support (0 = not supported, 1 = supported).
36 PWRCTL1/BATEN1 bidirectional Downstream port 1 power control output sampled at reset deassertion to indicate battery charging support (0 = not supported, 1 = supported).
37 SDA/SMBDAT bidirectional I2C serial data or SMBus data bidirectional line; function determined by SMBUSz pin setting at reset deassertion.
38 SCL/SMBCLK bidirectional I2C serial clock or SMBus clock bidirectional line; function determined by SMBUSz pin setting at reset deassertion.
39 SMBUSz,SS_SUSPEND bidirectional I2C/SMBus mode select input (1 = I2C, 0 = SMBus) sampled at reset deassertion, or SuperSpeed upstream suspend status output when stsOutputEn enabled.
40 BBbmConfigured0/FULLAUTOz/FULLPWRMGMTz/SS_UP bidirectional Billboard bmConfigured[0] control in I2C mode, full auto or power management mode control in SMBus mode, or upstream SS connection indicator when stsOutputEn enabled.
41 PWRCTL_POL bidirectional Power control polarity selection input (0 = active low, 1 = active high) sampled at reset deassertion.
42 BBEN/GANGED,HS_UP bidirectional Billboard enable control in I2C mode, ganged or individual power control mode selection in SMBus mode sampled at reset deassertion, or upstream HS connection indicator when stsOutputEn enabled.
43 OVERCUR4z input Downstream port 4 over-current detection input with internal pull-up; low level indicates an overcurrent event.
44 OVERCUR3z input Downstream port 3 over-current detection input with internal pull-up; low level indicates an overcurrent event.
45 BBbmConfigured1/AUTOENz/HS_SUSPEND bidirectional Billboard bmConfigured[1] control in I2C mode, automatic mode enable control in SMBus mode, or upstream HS suspend indicator when stsOutputEn enabled.
46 OVERCUR1z input Downstream port 1 over-current detection input with internal pull-up; low level indicates an overcurrent event.
47 OVERCUR2z input Downstream port 2 over-current detection input with internal pull-up; low level indicates an overcurrent event.
48 USB_VBUS input Upstream port power monitor input; requires voltage divider with 90.9-kΩ ±1% resistor to VBUS and 10-kΩ ±1% resistor to ground.
49 TEST input Factory test pin requiring external 10-kΩ or stronger pull-down resistor to ground for normal operation.
50 GRSTz input Global power reset input with internal pull-up; brings all internal registers to default states and device is nonfunctional when asserted.
51 VDD power_in 1.1-V power supply input voltage.
52 VDD33 power_in 3.3-V power supply input voltage.
53 USB_DP_UP bidirectional USB High-speed differential transceiver positive terminal for upstream port.
54 USB_DM_UP bidirectional USB High-speed differential transceiver negative terminal for upstream port.
55 USB_SSTXP_UP output USB SuperSpeed transmitter differential pair positive terminal for upstream port.
56 USB_SSTXM_UP output USB SuperSpeed transmitter differential pair negative terminal for upstream port.
57 VDD power_in 1.1-V power supply input voltage.
58 USB_SSRXP_UP input USB SuperSpeed receiver differential pair positive terminal for upstream port.
59 USB_SSRXM_UP input USB SuperSpeed receiver differential pair negative terminal for upstream port.
60 NC unconnected No connect; leave floating.
61 XO output Crystal oscillator output; leave unconnected if external oscillator drives XI pin.
62 XI input Crystal oscillator input accepting external oscillator output or crystal with 1-MΩ feedback resistor to XO.
63 VDD33 power_in 3.3-V power supply input voltage.
64 USB_R1 input Precision resistor reference input; connect 9.53-kΩ ±1% resistor between this pin and ground.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64-EP(9x9)
Category Communication Interface Chip/UART/485/232
Pins 65

CAD (KiCad official)

  • Symbol: TUSB8044AIRGCR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: tusb8044airgcr-etched.step / tusb8044airgcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tusb8044airgcr.step / tusb8044airgcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (69 pp, sha256 57142228db173b28, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF