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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TUSB8043ARGCR

Texas Instruments · Global Sourcing Parts · VQFN-64-EP(9x9)

TUSB8043ARGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	USB_DP_DN1	bidirectional	USB High-speed differential transceiver (positive) for downstream port 1; differential impedance 90Ω ±10%.
2	USB_DM_DN1	bidirectional	USB High-speed differential transceiver (negative) for downstream port 1; differential impedance 90Ω ±10%.
3	USB_SSTXP_DN1	output	USB SuperSpeed transmitter differential pair (positive) for downstream port 1.
4	USB_SSTXM_DN1	output	USB SuperSpeed transmitter differential pair (negative) for downstream port 1.
5	VDD	power_in	1.1-V core power supply rail for internal logic.
6	USB_SSRXP_DN1	input	USB SuperSpeed receiver differential pair (positive) for downstream port 1.
7	USB_SSRXM_DN1	input	USB SuperSpeed receiver differential pair (negative) for downstream port 1.
8	VDD	power_in	1.1-V core power supply rail for internal logic.
9	USB_DP_DN2	bidirectional	USB High-speed differential transceiver (positive) for downstream port 2; differential impedance 90Ω ±10%.
10	USB_DM_DN2	bidirectional	USB High-speed differential transceiver (negative) for downstream port 2; differential impedance 90Ω ±10%.
11	USB_SSTXP_DN2	output	USB SuperSpeed transmitter differential pair (positive) for downstream port 2.
12	USB_SSTXM_DN2	output	USB SuperSpeed transmitter differential pair (negative) for downstream port 2.
13	VDD	power_in	1.1-V core power supply rail for internal logic.
14	USB_SSRXP_DN2	input	USB SuperSpeed receiver differential pair (positive) for downstream port 2.
15	USB_SSRXM_DN2	input	USB SuperSpeed receiver differential pair (negative) for downstream port 2.
16	VDD33	power_in	3.3-V I/O and analog power supply rail.
17	USB_DP_DN3	bidirectional	USB High-speed differential transceiver (positive) for downstream port 3; differential impedance 90Ω ±10%.
18	USB_DM_DN3	bidirectional	USB High-speed differential transceiver (negative) for downstream port 3; differential impedance 90Ω ±10%.
19	USB_SSTXP_DN3	output	USB SuperSpeed transmitter differential pair (positive) for downstream port 3.
20	USB_SSTXM_DN3	output	USB SuperSpeed transmitter differential pair (negative) for downstream port 3.
21	VDD	power_in	1.1-V core power supply rail for internal logic.
22	USB_SSRXP_DN3	input	USB SuperSpeed receiver differential pair (positive) for downstream port 3.
23	USB_SSRXM_DN3	input	USB SuperSpeed receiver differential pair (negative) for downstream port 3.
24	USB_DP_DN4	bidirectional	USB High-speed differential transceiver (positive) for downstream port 4; differential impedance 90Ω ±10%.
25	USB_DM_DN4	bidirectional	USB High-speed differential transceiver (negative) for downstream port 4; differential impedance 90Ω ±10%.
26	USB_SSTXP_DN4	output	USB SuperSpeed transmitter differential pair (positive) for downstream port 4.
27	USB_SSTXM_DN4	output	USB SuperSpeed transmitter differential pair (negative) for downstream port 4.
28	VDD	power_in	1.1-V core power supply rail for internal logic.
29	USB_SSRXP_DN4	input	USB SuperSpeed receiver differential pair (positive) for downstream port 4.
30	USB_SSRXM_DN4	input	USB SuperSpeed receiver differential pair (negative) for downstream port 4.
31	VDD	power_in	1.1-V core power supply rail for internal logic.
32	PWRCTL4/BATEN4	bidirectional	USB Port 4 Power On Control for Downstream Power/Battery Charging Enable; sampled at reset to determine battery charging support (0=disabled, 1=enabled), has internal pull-down.
33	PWRCTL3/BATEN3	bidirectional	USB Port 3 Power On Control for Downstream Power/Battery Charging Enable; sampled at reset to determine battery charging support (0=disabled, 1=enabled), has internal pull-down.
34	VDD33	power_in	3.3-V I/O and analog power supply rail.
35	PWRCTL2/BATEN2	bidirectional	USB Port 2 Power On Control for Downstream Power/Battery Charging Enable; sampled at reset to determine battery charging support (0=disabled, 1=enabled), has internal pull-down.
36	PWRCTL1/BATEN1	bidirectional	USB Port 1 Power On Control for Downstream Power/Battery Charging Enable; sampled at reset to determine battery charging support (0=disabled, 1=enabled), has internal pull-down.
37	SDA/SMBDAT	bidirectional	I2C data/SMBus data interface with function depending on SMBUSz pin state (1=I2C EEPROM, 0=SMBus host), open-drain with internal pull-down.
38	SCL/SMBCLK	bidirectional	I2C clock/SMBus clock interface with function depending on SMBUSz pin state (1=I2C EEPROM, 0=SMBus host), open-drain with internal pull-down.
39	SMBUSz/SS_SUSPEND	bidirectional	I2C/SMBus mode select sampled at reset (1=I2C mode, 0=SMBus mode); also outputs SuperSpeed USB suspend status after reset if stsOutputEn enabled, has internal pull-up.
40	FULLPWRMGMTz/SMBA1/SS_UP	bidirectional	Full power management enable sampled at reset (0=power switching enabled, 1=disabled); SMBus address bit 1; outputs SuperSpeed USB connection status if stsOutputEn enabled, has internal pull-down.
41	PWRCTL_POL	bidirectional	Power Control Polarity sampled at reset to set PWRCTL[4:1] polarity (0=active low, 1=active high), has internal pull-up.
42	GANGED/SMBA2/HS_UP	bidirectional	Ganged operation enable sampled at reset (0=individual power control, 1=ganged); SMBus address bit 2; outputs high-speed USB connection status if stsOutputEn enabled, has internal pull-down.
43	OVERCUR4z	input	USB Port 4 Over-Current Detection input active low (0=overcurrent event, 1=normal), has internal pull-up.
44	OVERCUR3z	input	USB Port 3 Over-Current Detection input active low (0=overcurrent event, 1=normal), has internal pull-up.
45	AUTOENz/HS_SUSPEND	bidirectional	Automatic Charge Mode Enable sampled at reset (0=auto mode enabled for battery charging ports, 1=disabled); also outputs high-speed USB suspend status if stsOutputEn enabled, has internal pull-up.
46	OVERCUR1z	input	USB Port 1 Over-Current Detection input active low (0=overcurrent event, 1=normal), has internal pull-up.
47	OVERCUR2z	input	USB Port 2 Over-Current Detection input active low (0=overcurrent event, 1=normal), has internal pull-up.
48	USB_VBUS	input	USB upstream port power monitor input; VBUS detection requires voltage divider with 90.9-kΩ ±1% resistor to VBUS and 10-kΩ ±1% resistor to ground.
49	TEST	input	Factory test pin reserved for factory use; requires external 10-kΩ or stronger pull-down resistor to ground for normal operation.
50	GRSTz	input	Global power reset active low input that brings all internal registers to default states; when asserted, device is nonfunctional, has internal pull-up.
51	VDD	power_in	1.1-V core power supply rail for internal logic.
52	VDD33	power_in	3.3-V I/O and analog power supply rail.
53	USB_DP_UP	bidirectional	USB High-speed differential transceiver (positive) for upstream port; differential impedance 90Ω ±10%.
54	USB_DM_UP	bidirectional	USB High-speed differential transceiver (negative) for upstream port; differential impedance 90Ω ±10%.
55	USB_SSTXP_UP	output	USB SuperSpeed transmitter differential pair (positive) for upstream port.
56	USB_SSTXM_UP	output	USB SuperSpeed transmitter differential pair (negative) for upstream port.
57	VDD	power_in	1.1-V core power supply rail for internal logic.
58	USB_SSRXP_UP	input	USB SuperSpeed receiver differential pair (positive) for upstream port.
59	USB_SSRXM_UP	input	USB SuperSpeed receiver differential pair (negative) for upstream port.
60	NC	unconnected	No connect; leave floating.
61	XO	output	Crystal output for internal oscillator; may be left unconnected if external oscillator drives XI; requires 1-MΩ feedback resistor to XI when using crystal.
62	XI	input	Crystal input for internal oscillator or external clock input; requires 1-MΩ feedback resistor to XO when using crystal; external clock should have ±100 PPM stability.
63	VDD33	power_in	3.3-V I/O and analog power supply rail.
64	USB_R1	input	Precision resistor reference requiring 9.53-kΩ ±1% resistor connected between this pin and ground.
65	VSS	power_in	Ground connection with 6.0-mm x 6.0-mm thermal pad; thermal pad must be soldered to PCB ground plane via vias for thermal and mechanical performance.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-64-EP(9x9)
Category	Global Sourcing Parts
Pins	65

CAD (KiCad official)

Symbol: TUSB8043ARGCR
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
3D model files: tusb8043argcr-etched.step / tusb8043argcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tusb8043argcr.step / tusb8043argcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (62 pp, sha256 4b6e58175d875814, retrieved 2026-09-23, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF