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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TUSB8042ARGCT

Texas Instruments · USB Converters · QFN-64-EP(9x9)

TUSB8042ARGCT from Texas Instruments, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	USB_DP_DN1	bidirectional	USB 2.0 high-speed differential transceiver, positive side, for downstream port 1.
2	USB_DM_DN1	bidirectional	USB 2.0 high-speed differential transceiver, negative side, for downstream port 1.
3	USB_SSTXP_DN1	output	USB SuperSpeed transmitter differential pair, positive side, for downstream port 1.
4	USB_SSTXM_DN1	output	USB SuperSpeed transmitter differential pair, negative side, for downstream port 1.
5	VDD	power_in	1.1 V core supply rail (recommended 0.99 V to 1.26 V, nominal 1.1 V); VDD and VDD33 are to be implemented as a single power plane.
6	USB_SSRXP_DN1	input	USB SuperSpeed receiver differential pair, positive side, for downstream port 1.
7	USB_SSRXM_DN1	input	USB SuperSpeed receiver differential pair, negative side, for downstream port 1.
8	VDD	power_in	1.1 V core supply rail (recommended 0.99 V to 1.26 V, nominal 1.1 V).
9	USB_DP_DN2	bidirectional	USB 2.0 high-speed differential transceiver, positive side, for downstream port 2.
10	USB_DM_DN2	bidirectional	USB 2.0 high-speed differential transceiver, negative side, for downstream port 2.
11	USB_SSTXP_DN2	output	USB SuperSpeed transmitter differential pair, positive side, for downstream port 2.
12	USB_SSTXM_DN2	output	USB SuperSpeed transmitter differential pair, negative side, for downstream port 2.
13	VDD	power_in	1.1 V core supply rail (recommended 0.99 V to 1.26 V, nominal 1.1 V).
14	USB_SSRXP_DN2	input	USB SuperSpeed receiver differential pair, positive side, for downstream port 2.
15	USB_SSRXM_DN2	input	USB SuperSpeed receiver differential pair, negative side, for downstream port 2.
16	VDD33	power_in	3.3 V I/O supply rail (recommended 3.0 V to 3.6 V, nominal 3.3 V).
17	USB_DP_DN3	bidirectional	USB 2.0 high-speed differential transceiver, positive side, for downstream port 3.
18	USB_DM_DN3	bidirectional	USB 2.0 high-speed differential transceiver, negative side, for downstream port 3.
19	USB_SSTXP_DN3	output	USB SuperSpeed transmitter differential pair, positive side, for downstream port 3.
20	USB_SSTXM_DN3	output	USB SuperSpeed transmitter differential pair, negative side, for downstream port 3.
21	VDD	power_in	1.1 V core supply rail (recommended 0.99 V to 1.26 V, nominal 1.1 V).
22	USB_SSRXP_DN3	input	USB SuperSpeed receiver differential pair, positive side, for downstream port 3.
23	USB_SSRXM_DN3	input	USB SuperSpeed receiver differential pair, negative side, for downstream port 3.
24	USB_DP_DN4	bidirectional	USB 2.0 high-speed differential transceiver, positive side, for downstream port 4.
25	USB_DM_DN4	bidirectional	USB 2.0 high-speed differential transceiver, negative side, for downstream port 4.
26	USB_SSTXP_DN4	output	USB SuperSpeed transmitter differential pair, positive side, for downstream port 4.
27	USB_SSTXM_DN4	output	USB SuperSpeed transmitter differential pair, negative side, for downstream port 4.
28	VDD	power_in	1.1 V core supply rail (recommended 0.99 V to 1.26 V, nominal 1.1 V).
29	USB_SSRXP_DN4	input	USB SuperSpeed receiver differential pair, positive side, for downstream port 4.
30	USB_SSRXM_DN4	input	USB SuperSpeed receiver differential pair, negative side, for downstream port 4.
31	VDD	power_in	1.1 V core supply rail (recommended 0.99 V to 1.26 V, nominal 1.1 V).
32	PWRCTL4/BATEN4	bidirectional	Port 4 power-control output for the downstream VBUS power switch; sampled at reset release to set port 4 battery-charging support (0 = not supported, 1 = supported).
33	PWRCTL3/BATEN3	bidirectional	Port 3 power-control output for the downstream VBUS power switch; sampled at reset release to set port 3 battery-charging support (0 = not supported, 1 = supported).
34	VDD33	power_in	3.3 V I/O supply rail (recommended 3.0 V to 3.6 V, nominal 3.3 V).
35	PWRCTL2/BATEN2	bidirectional	Port 2 power-control output for the downstream VBUS power switch; sampled at reset release to set port 2 battery-charging support (0 = not supported, 1 = supported).
36	PWRCTL1/BATEN1	bidirectional	Port 1 power-control output for the downstream VBUS power switch; sampled at reset release to set port 1 battery-charging support (0 = not supported, 1 = supported).
37	SDA/SMBDAT	bidirectional	I2C data for the EEPROM interface when SMBUSz = 1, or SMBus data for an SMBus host when SMBUSz = 0; may be left unconnected if the external interface is not implemented.
38	SCL/SMBCLK	bidirectional	I2C clock for the EEPROM interface when SMBUSz = 1, or SMBus clock for an SMBus host when SMBUSz = 0; may be left unconnected if the external interface is not implemented.
39	SMBUSz/SS_SUSPEND	bidirectional	Sampled at reset release to select I2C mode (1) or SMBus mode (0); after reset, indicates upstream SuperSpeed suspend state when stsOutputEn is enabled, where 1 means suspended.
40	FULLPWRMGMTz/SMBA1/SS_UP	bidirectional	Sampled at reset release to enable full power management (0 = power-switch and overcurrent inputs supported, 1 = not supported); also SMBus address bit 1 in SMBus mode and upstream SuperSpeed connection status after reset.
41	PWRCTL_POL	bidirectional	Sampled at reset release to set the PWRCTL[4:1] polarity (0 = active low, 1 = active high).
42	GANGED/SMBA2/HS_UP	bidirectional	Sampled at reset release to select individual (0) or ganged (1) power-switch control; also SMBus address bit 2 in SMBus mode and upstream high-speed connection status after reset.
43	OVERCUR4z	input	Port 4 overcurrent input from the downstream power switch; 0 = overcurrent event occurred, 1 = no overcurrent event.
44	OVERCUR3z	input	Port 3 overcurrent input from the downstream power switch; 0 = overcurrent event occurred, 1 = no overcurrent event.
45	AUTOENz/HS_SUSPEND	bidirectional	Sampled at reset release to enable automatic charging mode (0 = enabled on battery-charging ports when hub is not connected, 1 = disabled); after reset, indicates upstream high-speed suspend state when stsOutputEn is enabled.
46	OVERCUR1z	input	Port 1 overcurrent input from the downstream power switch; 0 = overcurrent event occurred, 1 = no overcurrent event.
47	OVERCUR2z	input	Port 2 overcurrent input from the downstream power switch; 0 = overcurrent event occurred, 1 = no overcurrent event.
48	USB_VBUS	input	Upstream port VBUS monitor input, which must be connected to VBUS through a 90.9 kΩ ±1% resistor and to ground through a 10 kΩ ±1% resistor; voltage at this terminal is 0 to 1.155 V.
49	TEST	input	Reserved for factory test; in normal operation it requires an external resistor on the PCB to ground, with 10 kΩ or larger recommended.
50	GRSTz	input	Global power reset that restores all internal registers to default; the device is completely nonfunctional while asserted, and reset must last at least 3 ms from supplies being in range to release.
51	VDD	power_in	1.1 V core supply rail (recommended 0.99 V to 1.26 V, nominal 1.1 V).
52	VDD33	power_in	3.3 V I/O supply rail (recommended 3.0 V to 3.6 V, nominal 3.3 V).
53	USB_DP_UP	bidirectional	USB 2.0 high-speed differential transceiver, positive side, for the upstream port.
54	USB_DM_UP	bidirectional	USB 2.0 high-speed differential transceiver, negative side, for the upstream port.
55	USB_SSTXP_UP	output	USB SuperSpeed transmitter differential pair, positive side, for the upstream port.
56	USB_SSTXM_UP	output	USB SuperSpeed transmitter differential pair, negative side, for the upstream port.
57	VDD	power_in	1.1 V core supply rail (recommended 0.99 V to 1.26 V, nominal 1.1 V).
58	USB_SSRXP_UP	input	USB SuperSpeed receiver differential pair, positive side, for the upstream port.
59	USB_SSRXM_UP	input	USB SuperSpeed receiver differential pair, negative side, for the upstream port.
60	NC	unconnected	Not connected; leave floating.
61	XO	output	Crystal output of the internal oscillator; may be left unconnected if XI is driven by an external oscillator, and a 1 MΩ feedback resistor is required between XI and XO when a crystal is used.
62	XI	input	Crystal input of the internal oscillator, which may alternatively be driven by an external oscillator output; a 1 MΩ feedback resistor is required between XI and XO when a crystal is used.
63	VDD33	power_in	3.3 V I/O supply rail (recommended 3.0 V to 3.6 V, nominal 3.3 V).
64	USB_R1	input	Precision resistor reference; a 9.53 kΩ ±1% resistor must be connected between USB_R1 and GND.
65	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	QFN-64-EP(9x9)
Category	Interface
Pins	65

CAD (KiCad official)

Symbol: TUSB8042ARGCT
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
3D model files: tusb8042argct-etched.step / tusb8042argct-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tusb8042argct.step / tusb8042argct.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (64 pp, sha256 02efcabe88f32138, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF