TUSB8042ARGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	USB_DP_DN1	bidirectional	USB 2.0 high-speed differential transceiver (positive) for downstream port 1.
2	USB_DM_DN1	bidirectional	USB 2.0 high-speed differential transceiver (negative) for downstream port 1.
3	USB_SSTXP_DN1	output	USB SuperSpeed transmitter differential pair (positive) for downstream port 1.
4	USB_SSTXM_DN1	output	USB SuperSpeed transmitter differential pair (negative) for downstream port 1.
5	VDD	power_in	1.1 V (nominal) core power rail; recommended operating range 0.99 V to 1.26 V.
6	USB_SSRXP_DN1	input	USB SuperSpeed receiver differential pair (positive) for downstream port 1.
7	USB_SSRXM_DN1	input	USB SuperSpeed receiver differential pair (negative) for downstream port 1.
8	VDD	power_in	1.1 V (nominal) core power rail; recommended operating range 0.99 V to 1.26 V.
9	USB_DP_DN2	bidirectional	USB 2.0 high-speed differential transceiver (positive) for downstream port 2.
10	USB_DM_DN2	bidirectional	USB 2.0 high-speed differential transceiver (negative) for downstream port 2.
11	USB_SSTXP_DN2	output	USB SuperSpeed transmitter differential pair (positive) for downstream port 2.
12	USB_SSTXM_DN2	output	USB SuperSpeed transmitter differential pair (negative) for downstream port 2.
13	VDD	power_in	1.1 V (nominal) core power rail; recommended operating range 0.99 V to 1.26 V.
14	USB_SSRXP_DN2	input	USB SuperSpeed receiver differential pair (positive) for downstream port 2.
15	USB_SSRXM_DN2	input	USB SuperSpeed receiver differential pair (negative) for downstream port 2.
16	VDD33	power_in	3.3 V I/O and analog power rail; recommended operating range 3.0 V to 3.6 V.
17	USB_DP_DN3	bidirectional	USB 2.0 high-speed differential transceiver (positive) for downstream port 3.
18	USB_DM_DN3	bidirectional	USB 2.0 high-speed differential transceiver (negative) for downstream port 3.
19	USB_SSTXP_DN3	output	USB SuperSpeed transmitter differential pair (positive) for downstream port 3.
20	USB_SSTXM_DN3	output	USB SuperSpeed transmitter differential pair (negative) for downstream port 3.
21	VDD	power_in	1.1 V (nominal) core power rail; recommended operating range 0.99 V to 1.26 V.
22	USB_SSRXP_DN3	input	USB SuperSpeed receiver differential pair (positive) for downstream port 3.
23	USB_SSRXM_DN3	input	USB SuperSpeed receiver differential pair (negative) for downstream port 3.
24	USB_DP_DN4	bidirectional	USB 2.0 high-speed differential transceiver (positive) for downstream port 4.
25	USB_DM_DN4	bidirectional	USB 2.0 high-speed differential transceiver (negative) for downstream port 4.
26	USB_SSTXP_DN4	output	USB SuperSpeed transmitter differential pair (positive) for downstream port 4.
27	USB_SSTXM_DN4	output	USB SuperSpeed transmitter differential pair (negative) for downstream port 4.
28	VDD	power_in	1.1 V (nominal) core power rail; recommended operating range 0.99 V to 1.26 V.
29	USB_SSRXP_DN4	input	USB SuperSpeed receiver differential pair (positive) for downstream port 4.
30	USB_SSRXM_DN4	input	USB SuperSpeed receiver differential pair (negative) for downstream port 4.
31	VDD	power_in	1.1 V (nominal) core power rail; recommended operating range 0.99 V to 1.26 V.
32	PWRCTL4/BATEN4	bidirectional	Port 4 power-control output for the downstream power switch and battery-charging enable sampled at reset; leave unconnected if power management is not implemented.
33	PWRCTL3/BATEN3	bidirectional	Port 3 power-control output for the downstream power switch and battery-charging enable sampled at reset; leave unconnected if power management is not implemented.
34	VDD33	power_in	3.3 V I/O and analog power rail; recommended operating range 3.0 V to 3.6 V.
35	PWRCTL2/BATEN2	bidirectional	Port 2 power-control output for the downstream power switch and battery-charging enable sampled at reset; leave unconnected if power management is not implemented.
36	PWRCTL1/BATEN1	bidirectional	Port 1 power-control output for the downstream power switch and battery-charging enable sampled at reset; leave unconnected if power management is not implemented.
37	SDA/SMBDAT	bidirectional	I2C data (EEPROM interface when SMBUSz = 1) or SMBus host data (when SMBUSz = 0); leave unconnected if the external interface is not implemented.
38	SCL/SMBCLK	bidirectional	I2C clock (EEPROM interface when SMBUSz = 1) or SMBus host clock (when SMBUSz = 0); leave unconnected if the external interface is not implemented.
39	SMBUSz/SS_SUSPEND	bidirectional	I2C/SMBus mode select sampled at reset (1 = I2C, 0 = SMBus); after reset it indicates the upstream SuperSpeed suspend state when enabled through stsOutputEn.
40	FULLPWRMGMTz/SMBA1/SS_UP	bidirectional	Full power-management enable sampled at reset (0 = power switch and overcurrent inputs supported, 1 = not supported); SMBus address bit 1 in SMBus mode; after reset it indicates upstream SuperSpeed connection when enabled.
41	PWRCTL_POL	bidirectional	Power-control polarity sampled at reset for PWRCTL[4:1] (0 = active low, 1 = active high).
42	GANGED/SMBA2/HS_UP	bidirectional	Ganged power-control enable sampled at reset (0 = individual port control, 1 = ganged control); SMBus address bit 2 in SMBus mode; after reset it indicates upstream high-speed connection when enabled.
43	OVERCUR4z	input	Port 4 overcurrent input, normally driven by the port 4 power switch (0 = overcurrent event, 1 = no overcurrent); may be left unconnected if another OVERCURz pin is used in ganged mode.
44	OVERCUR3z	input	Port 3 overcurrent input, normally driven by the port 3 power switch (0 = overcurrent event, 1 = no overcurrent); may be left unconnected if another OVERCURz pin is used in ganged mode.
45	AUTOENz/HS_SUSPEND	bidirectional	Automatic charging mode enable sampled at reset (0 = enabled on battery-charging ports when the hub is not connected, 1 = disabled); after reset it indicates upstream high-speed suspend when enabled through stsOutputEn.
46	OVERCUR1z	input	Port 1 overcurrent input, normally driven by the port 1 power switch (0 = overcurrent event, 1 = no overcurrent); may be left unconnected if another OVERCURz pin is used in ganged mode.
47	OVERCUR2z	input	Port 2 overcurrent input, normally driven by the port 2 power switch (0 = overcurrent event, 1 = no overcurrent); may be left unconnected if another OVERCURz pin is used in ganged mode.
48	USB_VBUS	input	Upstream port VBUS monitor that must be fed through a divider (90.9 kΩ ±1% to VBUS and 10 kΩ ±1% to GND); the terminal voltage is limited to 0 to 1.155 V.
49	TEST	input	Reserved for factory test; during normal operation it requires an external 10 kΩ or larger resistor on the PCB.
50	GRSTz	input	Active-low global power-on reset that restores all internal registers to default; the device is non-functional while asserted and reset must last at least 3 ms after the supplies are stable.
51	VDD	power_in	1.1 V (nominal) core power rail; recommended operating range 0.99 V to 1.26 V.
52	VDD33	power_in	3.3 V I/O and analog power rail; recommended operating range 3.0 V to 3.6 V.
53	USB_DP_UP	bidirectional	USB 2.0 high-speed differential transceiver (positive) for the upstream port.
54	USB_DM_UP	bidirectional	USB 2.0 high-speed differential transceiver (negative) for the upstream port.
55	USB_SSTXP_UP	output	USB SuperSpeed transmitter differential pair (positive) for the upstream port.
56	USB_SSTXM_UP	output	USB SuperSpeed transmitter differential pair (negative) for the upstream port.
57	VDD	power_in	1.1 V (nominal) core power rail; recommended operating range 0.99 V to 1.26 V.
58	USB_SSRXP_UP	input	USB SuperSpeed receiver differential pair (positive) for the upstream port.
59	USB_SSRXM_UP	input	USB SuperSpeed receiver differential pair (negative) for the upstream port.
60	NC	unconnected	No connection; leave floating.
61	XO	output	Crystal output of the internal oscillator; may be left unconnected if XI is driven by an external oscillator, and a 1 MΩ feedback resistor is required between XI and XO when a crystal is used.
62	XI	input	Crystal input of the internal oscillator that can also be driven by an external oscillator; a 1 MΩ feedback resistor is required between XI and XO when a crystal is used.
63	VDD33	power_in	3.3 V I/O and analog power rail; recommended operating range 3.0 V to 3.6 V.
64	USB_R1	input	Precision resistor reference; connect a 9.53 kΩ ±1% resistor between USB_R1 and GND.
65	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-64-EP(9x9)
Category	Communication Interface Chip/UART/485/232
Pins	65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VDD supply voltage range	VDD	-0.3		1.4	V		10
VDD33 supply voltage range	VDD33	-0.3		3.8	V		10
Voltage at USB_SSRXP_UP, USB_SSRXN_UP, SSRXP_DN[4:1], USB_RXN_DP[4:1] and USB_VBUS terminals		-0.3		1.4	V		10
Voltage at XI terminal		-0.3		2.45	V		10
Voltage at all other terminals		-0.3		3.8	V		10
Storage temperature	Tstg	-65		150	°C		10
ESD human body model (HBM)	V(ESD)	-2000		2000	V	HBM per ANSI/ESDA/JEDEC JS-001, all pins	10
ESD charged device model (CDM)	V(ESD)	-500		500	V	CDM per ANSI/ESDA/JEDEC JS-002, all pins	10
VDD 1.1V supply voltage	VDD	0.99	1.1	1.26	V		10
VDD33 3.3V supply voltage	VDD33	3	3.3	3.6	V		10
Voltage at USB_VBUS terminal	USB_VBUS	0		1.155	V		10
TUSB8042A ambient temperature	TA	0		70	°C		10
Junction temperature	TJ	-40		105	°C		10
High-level input voltage (3.3V I/O)	VIH	2		3.6	V		12
Low-level input voltage (3.3V I/O)	VIL	0		0.8	V		12
Input voltage (3.3V I/O)	VI	0		3.6	V		12
Junction-to-ambient thermal resistance, RGC 64-pin	RθJA		26		°C/W		10
Junction-to-case (top) thermal resistance, RGC 64-pin	RθJC(top)		11.5		°C/W		10
Junction-to-board thermal resistance, RGC 64-pin	RθJB		5.3		°C/W		10
Junction-to-top characterization parameter, RGC 64-pin	ΨJT		0.2		°C/W		10
Junction-to-board characterization parameter, RGC 64-pin	ΨJB		5.2		°C/W		10
Junction-to-case (bottom) thermal resistance, RGC 64-pin	RθJC(bot)		1		°C/W		11

CAD (KiCad official)

Symbol: TUSB8042ARGCR
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
3D model files: tusb8042argcr-etched.step / tusb8042argcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tusb8042argcr.step / tusb8042argcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (64 pp, sha256 02efcabe88f32138, retrieved 2026-10-31, tier: manufacturer)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

TUSB8042ARGCR

Verified TUSB8042ARGCR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README