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TUSB8041IRGCR

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Texas Instruments USB ICs, QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TUSB8041IRGCR

Texas Instruments · USB ICs · QFN-64-EP(9x9)

TUSB8041IRGCR from Texas Instruments, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 USB_DP_DN1 bidirectional USB High-speed differential transceiver (positive) for downstream port 1.
2 USB_DM_DN1 bidirectional USB High-speed differential transceiver (negative) for downstream port 1.
3 USB_SSTXP_DN1 output USB SuperSpeed transmitter differential pair (positive) for downstream port 1.
4 USB_SSTXM_DN1 output USB SuperSpeed transmitter differential pair (negative) for downstream port 1.
5 VDD power_in 1.1-V power rail.
6 USB_SSRXP_DN1 input USB SuperSpeed receiver differential pair (positive) for downstream port 1.
7 USB_SSRXM_DN1 input USB SuperSpeed receiver differential pair (negative) for downstream port 1.
8 VDD power_in 1.1-V power rail.
9 USB_DP_DN2 bidirectional USB High-speed differential transceiver (positive) for downstream port 2.
10 USB_DM_DN2 bidirectional USB High-speed differential transceiver (negative) for downstream port 2.
11 USB_SSTXP_DN2 output USB SuperSpeed transmitter differential pair (positive) for downstream port 2.
12 USB_SSTXM_DN2 output USB SuperSpeed transmitter differential pair (negative) for downstream port 2.
13 VDD power_in 1.1-V power rail.
14 USB_SSRXP_DN2 input USB SuperSpeed receiver differential pair (positive) for downstream port 2.
15 USB_SSRXM_DN2 input USB SuperSpeed receiver differential pair (negative) for downstream port 2.
16 VDD33 power_in 3.3-V power rail.
17 USB_DP_DN3 bidirectional USB High-speed differential transceiver (positive) for downstream port 3.
18 USB_DM_DN3 bidirectional USB High-speed differential transceiver (negative) for downstream port 3.
19 USB_SSTXP_DN3 output USB SuperSpeed transmitter differential pair (positive) for downstream port 3.
20 USB_SSTXM_DN3 output USB SuperSpeed transmitter differential pair (negative) for downstream port 3.
21 VDD power_in 1.1-V power rail.
22 USB_SSRXP_DN3 input USB SuperSpeed receiver differential pair (positive) for downstream port 3.
23 USB_SSRXM_DN3 input USB SuperSpeed receiver differential pair (negative) for downstream port 3.
24 USB_DP_DN4 bidirectional USB High-speed differential transceiver (positive) for downstream port 4.
25 USB_DM_DN4 bidirectional USB High-speed differential transceiver (negative) for downstream port 4.
26 USB_SSTXP_DN4 output USB SuperSpeed transmitter differential pair (positive) for downstream port 4.
27 USB_SSTXM_DN4 output USB SuperSpeed transmitter differential pair (negative) for downstream port 4.
28 VDD power_in 1.1-V power rail.
29 USB_SSRXP_DN4 input USB SuperSpeed receiver differential pair (positive) for downstream port 4.
30 USB_SSRXM_DN4 input USB SuperSpeed receiver differential pair (negative) for downstream port 4.
31 VDD power_in 1.1-V power rail.
32 PWRCTL4/BATEN4 bidirectional USB Port 4 power-on control for the downstream power switch, sampled at reset de-assertion to set Port 4 battery charging support (0 = not supported, 1 = supported); internal pull-down.
33 PWRCTL3/BATEN3 bidirectional USB Port 3 power-on control for the downstream power switch, sampled at reset de-assertion to set Port 3 battery charging support (0 = not supported, 1 = supported); internal pull-down.
34 VDD33 power_in 3.3-V power rail.
35 PWRCTL2/BATEN2 bidirectional USB Port 2 power-on control for the downstream power switch, sampled at reset de-assertion to set Port 2 battery charging support (0 = not supported, 1 = supported); internal pull-down.
36 PWRCTL1/BATEN1 bidirectional USB Port 1 power-on control for the downstream power switch, sampled at reset de-assertion to set Port 1 battery charging support (0 = not supported, 1 = supported); internal pull-down.
37 SDA/SMBDAT bidirectional I2C/SMBus data, serial data interface for an I2C EEPROM (SMBUSz = 1) or SMBus host (SMBUSz = 0); internal pull-down, can be left unconnected if no external interface.
38 SCL/SMBCLK bidirectional I2C/SMBus clock, serial clock interface for an I2C EEPROM (SMBUSz = 1) or SMBus host (SMBUSz = 0); internal pull-down, can be left unconnected if no external interface.
39 SMBUSz/SS_SUSPEND bidirectional I2C/SMBus mode select sampled at reset de-assertion (1 = I2C, 0 = SMBus), and SuperSpeed suspend status after reset if enabled; internal pull-up.
40 FULLPWRMGMTz/SMBA1/SS_UP bidirectional Full power management enable sampled at reset (0 = power switching and over-current inputs supported, 1 = not supported), SMBus address bit 1, and SuperSpeed upstream connection status after reset; internal pull-down.
41 PWRCTL_POL bidirectional Power control polarity sampled at reset de-assertion for PWRCTL[4:1] (0 = active low, 1 = active high); internal pull-up.
42 GANGED/SMBA2/HS_UP bidirectional Ganged operation enable sampled at reset (0 = individual power control, 1 = ganged), SMBus address bit 2, and High-speed upstream connection status after reset; internal pull-down.
43 OVERCUR4z input USB Port 4 over-current detection input (0 = over-current event occurred, 1 = none); internal pull-up, can be left unconnected if power management is not implemented.
44 OVERCUR3z input USB Port 3 over-current detection input (0 = over-current event occurred, 1 = none); internal pull-up, can be left unconnected if power management is not implemented.
45 AUTOENz/HS_SUSPEND bidirectional Automatic charge mode enable sampled at reset (0 = automatic mode enabled, 1 = disabled) and High-speed suspend status after reset; internal pull-up.
46 OVERCUR1z input USB Port 1 over-current detection input (0 = over-current event occurred, 1 = none); internal pull-up, can be left unconnected if power management is not implemented.
47 OVERCUR2z input USB Port 2 over-current detection input (0 = over-current event occurred, 1 = none); internal pull-up, can be left unconnected if power management is not implemented.
48 USB_VBUS input USB upstream port power monitor; connect to VBUS through a 90.9-kΩ ±1% resistor and to ground through a 10-kΩ ±1% resistor.
49 TEST input Reserved for factory test; internal pull-down.
50 GRSTz input Global power reset that brings all internal registers to default states; device is completely nonfunctional while asserted; internal pull-up.
51 VDD power_in 1.1-V power rail.
52 VDD33 power_in 3.3-V power rail.
53 USB_DP_UP bidirectional USB High-speed differential transceiver (positive) for the upstream port.
54 USB_DM_UP bidirectional USB High-speed differential transceiver (negative) for the upstream port.
55 USB_SSTXP_UP output USB SuperSpeed transmitter differential pair (positive) for the upstream port.
56 USB_SSTXM_UP output USB SuperSpeed transmitter differential pair (negative) for the upstream port.
57 VDD power_in 1.1-V power rail.
58 USB_SSRXP_UP input USB SuperSpeed receiver differential pair (positive) for the upstream port.
59 USB_SSRXM_UP input USB SuperSpeed receiver differential pair (negative) for the upstream port.
60 NC unconnected No connect, leave floating.
61 XO output Crystal output of the internal oscillator; may be left unconnected if XI is driven by an external oscillator; 1-MΩ feedback resistor required between XI and XO with a crystal.
62 XI input Crystal input for the internal oscillator, or driven by an external oscillator output; 1-MΩ feedback resistor required between XI and XO with a crystal.
63 VDD33 power_in 3.3-V power rail.
64 USB_R1 input Precision resistor reference; connect a 9.53-kΩ ±1% resistor between USB_R1 and GND.
65 VSS power_in Ground; the thermal pad must be connected to ground.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-64-EP(9x9)
Category Interface ICs
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD steady-state VDD -0.3 1.4 V Steady-state supply voltage 9
Supply voltage VDD33 steady-state VDD33 -0.3 3.8 V Steady-state supply voltage 9
Voltage range, USB SS RX and USB_VBUS terminals -0.3 1.4 V USB_SSRXP_UP, USB_SSRXN_UP, USB_SSRXP_DN[4:1], USB_SSRXN_DP[4:1], USB_VBUS 9
Voltage range, XI terminals -0.3 2.45 V XI terminals 9
Voltage range, all other terminals -0.3 3.8 V All other terminals 9
Storage temperature Tstg -65 150 °C 9
ESD HBM V(ESD) -2000 2000 V Human body model, ANSI/ESDA/JEDEC JS-001 9
ESD CDM V(ESD) -500 500 V Charged device model, JESD22-C101 9
1.1V supply voltage VDD 0.99 1.1 1.26 V 9
3.3V supply voltage VDD33 3 3.3 3.6 V 9
Voltage at USB_VBUS PAD USB_VBUS 0 1.155 V 9
Operating free-air temperature TA -40 85 °C TUSB8041I 9
Operating junction temperature TJ -40 105 °C 9
High-level input voltage VIH 2 V VDD33; max printed as VDD33 10
Low-level input voltage VIL 0 0.8 V VDD33 10
Low-level input voltage, JTAG pins only VIL 0 0.55 V JTAG pins only 10
Input voltage VI 0 V max printed as VDD33 10
Output voltage VO 0 V max printed as VDD33 10
Input transition time (trise and tfall) tt 0 25 ns 10
High-level output voltage VOH 2.4 V VDD33, IOH = -4 mA 10
Low-level output voltage VOL 0.4 V VDD33, IOL = 4 mA 10
High-impedance output current IOZ -20 20 µA VDD33, VI = 0 to VDD33 10
High-impedance output current with internal pullup or pulldown IOZP -250 250 µA VDD33, VI = 0 to VDD33 10
Input current II -15 15 µA VDD33, VI = 0 to VDD33 10
VDD and VDD33 stable before de-assertion of GRSTz td2 3 ms 11
Setup for MISC inputs tsu_io 0.1 µs Sampled at the de-assertion of GRSTz 11
Hold for MISC inputs thd_io 0.1 µs Sampled at the de-assertion of GRSTz 11
VDD33 supply ramp tVDD33_RAMP 0.2 100 ms 11
VDD supply ramp tVDD_RAMP 0.2 100 ms 11
Junction-to-ambient thermal resistance RθJA 26 °C/W RGC 64 pins 10
Junction-to-case (top) thermal resistance RθJCtop 11.5 °C/W RGC 64 pins 10
Junction-to-board thermal resistance RθJB 5.3 °C/W RGC 64 pins 10
Junction-to-top characterization parameter ψJT 0.2 °C/W RGC 64 pins 10
Junction-to-board characterization parameter ψJB 5.2 °C/W RGC 64 pins 10
Junction-to-case (bottom) thermal resistance RθJCbot 1 °C/W RGC 64 pins 10
VDD33 supply current, Power On (after Reset) 2.3 mA VDD33 3.3 V, TA = 25°C 11
VDD supply current, Power On (after Reset) 28 mA VDD 1.1 V, TA = 25°C 11
VDD33 supply current, Suspend 2.5 mA VDD33 3.3 V, TA = 25°C 11
VDD supply current, Suspend 33 mA VDD 1.1 V, TA = 25°C 11
VDD33 supply current, 3.0 host / 4 SS Devices and Hub in U0 49 mA VDD33 3.3 V, TA = 25°C 11
VDD supply current, 3.0 host / 4 SS Devices and Hub in U0 778 mA VDD 1.1 V, TA = 25°C 11
VDD33 supply current, 2.0 host / 4 HS Devices 76 mA VDD33 3.3 V, TA = 25°C 11
VDD supply current, 2.0 host / 4 HS Devices 86 mA VDD 1.1 V, TA = 25°C 11
VDD33 supply current, SMBUS Programming 79 mA VDD33 3.3 V, TA = 25°C 11
VDD supply current, SMBUS Programming 225 mA VDD 1.1 V, TA = 25°C 11

CAD (KiCad official)

  • Symbol: TUSB8041IRGCR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: tusb8041irgcr-etched.step / tusb8041irgcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tusb8041irgcr.step / tusb8041irgcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (50 pp, sha256 fbab35d6db2e54aa, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF