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TUSB8041IPAPRQ1

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Texas Instruments USB Converters, TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TUSB8041IPAPRQ1

Texas Instruments · USB Converters · TQFP-64(10x10)

TUSB8041IPAPRQ1 from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PWRCTL3/BATEN3 bidirectional USB Port 3 power on control for downstream power/battery charging enable; the value sampled at reset de-assertion sets Port 3 battery charging support (0 = not supported, 1 = supported).
2 VDD33 power_in 3.3-V power rail; recommended supply 3 V to 3.6 V (3.3 V nominal).
3 PWRCTL2/BATEN2 bidirectional USB Port 2 power on control for downstream power/battery charging enable; the value sampled at reset de-assertion sets Port 2 battery charging support (0 = not supported, 1 = supported).
4 PWRCTL1/BATEN1 bidirectional USB Port 1 power on control for downstream power/battery charging enable; the value sampled at reset de-assertion sets Port 1 battery charging support (0 = not supported, 1 = supported).
5 SDA/SMBDAT bidirectional I2C data (serial data for an I2C EEPROM when SMBUSz = 1) or SMBus data (for an SMBus host when SMBUSz = 0); may be left unconnected if the external interface is not implemented.
6 SCL/SMBCLK bidirectional I2C clock (serial clock for an I2C EEPROM when SMBUSz = 1) or SMBus clock (for an SMBus host when SMBUSz = 0); may be left unconnected if the external interface is not implemented.
7 SMBUSz/SS_SUSPEND bidirectional I2C/SMBus mode select sampled at reset (1 = I2C mode, 0 = SMBus mode); after reset it indicates the SuperSpeed USB suspend status of the upstream port when enabled (1 = suspended).
8 FULLPWRMGMTz/SMBA1/SS_UP bidirectional Full power management enable sampled at reset (0 = power switching and over-current inputs supported, 1 = not supported); SMBus address bit 1 in SMBus mode; after reset it indicates SuperSpeed upstream connection status when enabled. Power switching must be supported for battery charging applications.
9 PWRCTL_POL bidirectional Power control polarity sampled at reset de-assertion to set the polarity of PWRCTL[4:1] (0 = active low, 1 = active high).
10 GANGED/SMBA2/HS_UP bidirectional Ganged operation enable sampled at reset (0 = individual power control, 1 = power control gangs) when power switching is enabled; SMBus address bit 2 in SMBus mode; after reset it indicates the high-speed upstream connection status when enabled. Individual power control must be enabled for battery charging applications.
11 OVERCUR4z input USB Port 4 over-current detection input from the downstream port power switch (0 = over-current event has occurred); may be left unconnected if power management is not implemented.
12 OVERCUR3z input USB Port 3 over-current detection input from the downstream port power switch (0 = over-current event has occurred); may be left unconnected if power management is not implemented.
13 AUTOENz/HS_SUSPEND bidirectional Automatic charge mode enable sampled at reset (0 = automatic mode enabled on battery-charging ports when the hub is unconnected, 1 = disabled); after reset it indicates the high-speed upstream suspend status when enabled.
14 OVERCUR1z input USB Port 1 over-current detection input from the downstream port power switch (0 = over-current event has occurred); may be left unconnected if power management is not implemented.
15 OVERCUR2z input USB Port 2 over-current detection input from the downstream port power switch (0 = over-current event has occurred); may be left unconnected if power management is not implemented.
16 USB_VBUS input USB upstream port VBUS detection; must connect to VBUS through a 90.9 kΩ ±1% resistor and to ground through a 10 kΩ ±1% resistor (voltage divider), with 0 V to 1.155 V at the pad.
17 TEST input Reserved for factory test.
18 GRSTz input Global power reset that returns all internal registers to default states; when asserted the device is completely nonfunctional.
19 VDD power_in 1.1-V power rail; recommended supply 0.99 V to 1.26 V (1.1 V nominal).
20 VDD33 power_in 3.3-V power rail; recommended supply 3 V to 3.6 V (3.3 V nominal).
21 USB_DP_UP bidirectional USB high-speed differential transceiver (positive) for the upstream port.
22 USB_DM_UP bidirectional USB high-speed differential transceiver (negative) for the upstream port.
23 USB_SSTXP_UP output USB SuperSpeed transmitter differential pair (positive) for the upstream port.
24 USB_SSTXM_UP output USB SuperSpeed transmitter differential pair (negative) for the upstream port.
25 VDD power_in 1.1-V power rail; recommended supply 0.99 V to 1.26 V (1.1 V nominal).
26 USB_SSRXP_UP input USB SuperSpeed receiver differential pair (positive) for the upstream port.
27 USB_SSRXM_UP input USB SuperSpeed receiver differential pair (negative) for the upstream port.
28 NC unconnected No connect; leave floating.
29 XO output Crystal output for the internal oscillator; may be left unconnected if XI is driven by an external oscillator, and a 1-MΩ feedback resistor is required between XI and XO when using a crystal.
30 XI input Crystal input for the internal oscillator, which may alternately be driven by an external oscillator; a 1-MΩ feedback resistor is required between XI and XO when using a crystal (single 24-MHz clock input per the features list).
31 VDD33 power_in 3.3-V power rail; recommended supply 3 V to 3.6 V (3.3 V nominal).
32 USB_R1 input Precision resistor reference; a 9.53-kΩ ±1% resistor should be connected between USB_R1 and GND.
33 USB_DP_DN1 bidirectional USB high-speed differential transceiver (positive) for downstream Port 1.
34 USB_DM_DN1 bidirectional USB high-speed differential transceiver (negative) for downstream Port 1.
35 USB_SSTXP_DN1 output USB SuperSpeed transmitter differential pair (positive) for downstream Port 1.
36 USB_SSTXM_DN1 output USB SuperSpeed transmitter differential pair (negative) for downstream Port 1.
37 VDD power_in 1.1-V power rail; recommended supply 0.99 V to 1.26 V (1.1 V nominal).
38 USB_SSRXP_DN1 input USB SuperSpeed receiver differential pair (positive) for downstream Port 1.
39 USB_SSRXM_DN1 input USB SuperSpeed receiver differential pair (negative) for downstream Port 1.
40 NC unconnected No connect; leave floating.
41 USB_DP_DN2 bidirectional USB high-speed differential transceiver (positive) for downstream Port 2.
42 USB_DM_DN2 bidirectional USB high-speed differential transceiver (negative) for downstream Port 2.
43 USB_SSTXP_DN2 output USB SuperSpeed transmitter differential pair (positive) for downstream Port 2.
44 USB_SSTXM_DN2 output USB SuperSpeed transmitter differential pair (negative) for downstream Port 2.
45 VDD power_in 1.1-V power rail; recommended supply 0.99 V to 1.26 V (1.1 V nominal).
46 USB_SSRXP_DN2 input USB SuperSpeed receiver differential pair (positive) for downstream Port 2.
47 USB_SSRXM_DN2 input USB SuperSpeed receiver differential pair (negative) for downstream Port 2.
48 VDD33 power_in 3.3-V power rail; recommended supply 3 V to 3.6 V (3.3 V nominal).
49 USB_DP_DN3 bidirectional USB high-speed differential transceiver (positive) for downstream Port 3.
50 USB_DM_DN3 bidirectional USB high-speed differential transceiver (negative) for downstream Port 3.
51 USB_SSTXP_DN3 output USB SuperSpeed transmitter differential pair (positive) for downstream Port 3.
52 USB_SSTXM_DN3 output USB SuperSpeed transmitter differential pair (negative) for downstream Port 3.
53 VDD power_in 1.1-V power rail; recommended supply 0.99 V to 1.26 V (1.1 V nominal).
54 USB_SSRXP_DN3 input USB SuperSpeed receiver differential pair (positive) for downstream Port 3.
55 USB_SSRXM_DN3 input USB SuperSpeed receiver differential pair (negative) for downstream Port 3.
56 USB_DP_DN4 bidirectional USB high-speed differential transceiver (positive) for downstream Port 4.
57 USB_DM_DN4 bidirectional USB high-speed differential transceiver (negative) for downstream Port 4.
58 USB_SSTXP_DN4 output USB SuperSpeed transmitter differential pair (positive) for downstream Port 4.
59 USB_SSTXM_DN4 output USB SuperSpeed transmitter differential pair (negative) for downstream Port 4.
60 VDD power_in 1.1-V power rail; recommended supply 0.99 V to 1.26 V (1.1 V nominal).
61 USB_SSRXP_DN4 input USB SuperSpeed receiver differential pair (positive) for downstream Port 4.
62 USB_SSRXM_DN4 input USB SuperSpeed receiver differential pair (negative) for downstream Port 4.
63 VDD power_in 1.1-V power rail; recommended supply 0.99 V to 1.26 V (1.1 V nominal).
64 PWRCTL4/BATEN4 bidirectional USB Port 4 power on control for downstream power/battery charging enable; the value sampled at reset de-assertion sets Port 4 battery charging support (0 = not supported, 1 = supported).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-64(10x10)
Category Interface
Pins 64

CAD (KiCad official)

  • Symbol: TUSB8041IPAPRQ1
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: tusb8041ipaprq1-etched.step / tusb8041ipaprq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tusb8041ipaprq1.step / tusb8041ipaprq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (50 pp, sha256 28023494da9dcbf2, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF