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TUSB2077APTR

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Texas Instruments USB Converters, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TUSB2077APTR

Texas Instruments · USB Converters · LQFP-48(7x7)

TUSB2077APTR from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SUSPND output Suspend status output; active high during suspend mode, low for normal operation; 3-stated during low-power suspend.
2 DP0PUR tri_state Root port pullup resistor disable output; inactive (floating) for 15 ms after system reset or BUSPWR logic level change, then driven to VCC (3.3 V).
3 DP0 bidirectional Root port USB differential data plus; paired with DM0 to constitute the upstream USB port.
4 DM0 bidirectional Root port USB differential data minus; paired with DP0 to constitute the upstream USB port.
5 GND power_in Ground; must be tied to ground for proper operation.
6 RESET input Active low TTL input with hysteresis; initializes all logic when asserted at power up; recommended pulse width 100 μs to 1 ms after 3.3-V VCC reaches 90%.
7 EECLK tri_state EEPROM serial clock output; 3-state with 100-μA internal pulldown when EXTMEM is low; disabled and must be left floating when EXTMEM is high.
8 EEDATA/GANGED bidirectional When EXTMEM is high, selects ganged or per-port power overcurrent detection; when EXTMEM is low, acts as serial data I/O for EEPROM with 100-μA internal pulldown; must not change dynamically during operation.
9 VCC power_in 3.3-V supply voltage.
10 BUSPWR input Active-low power source indicator; indicates whether downstream ports source power from USB cable (pulled low) or local power supply (pulled to 3.3 V); input must not change dynamically during operation.
11 PWRON1 output Power-on/-off control signal for downstream port 1; active low, push-pull output that enables external power switch; cannot drive 5-V signals.
12 OVRCUR1 input Overcurrent input for downstream port 1; active low with noise filtering logic for immunity to voltage spikes.
13 DM1 bidirectional USB differential data minus for downstream port 1; paired with DP1 to support downstream USB port.
14 DP1 bidirectional USB differential data plus for downstream port 1; paired with DM1 to support downstream USB port.
15 PWRON2 output Power-on/-off control signal for downstream port 2; active low, push-pull output that enables external power switch.
16 OVRCUR2 input Overcurrent input for downstream port 2; active low with noise filtering logic.
17 DM2 bidirectional USB differential data minus for downstream port 2; paired with DP2 to support downstream USB port.
18 DP2 bidirectional USB differential data plus for downstream port 2; paired with DM2 to support downstream USB port.
19 PWRON3 output Power-on/-off control signal for downstream port 3; active low, push-pull output that enables external power switch.
20 OVRCUR3 input Overcurrent input for downstream port 3; active low with noise filtering logic.
21 DM3 bidirectional USB differential data minus for downstream port 3; paired with DP3 to support downstream USB port.
22 DP3 bidirectional USB differential data plus for downstream port 3; paired with DM3 to support downstream USB port.
23 PWRON4 output Power-on/-off control signal for downstream port 4; active low, push-pull output that enables external power switch.
24 GND power_in Ground; must be tied to ground for proper operation.
25 OVRCUR4 input Overcurrent input for downstream port 4; active low with noise filtering logic.
26 DM4 bidirectional USB differential data minus for downstream port 4; paired with DP4 to support downstream USB port.
27 DP4 bidirectional USB differential data plus for downstream port 4; paired with DM4 to support downstream USB port.
28 PWRON5 output Power-on/-off control signal for downstream port 5; active low, push-pull output that enables external power switch.
29 OVRCUR5 input Overcurrent input for downstream port 5; active low with noise filtering logic.
30 DM5 bidirectional USB differential data minus for downstream port 5; paired with DP5 to support downstream USB port.
31 DP5 bidirectional USB differential data plus for downstream port 5; paired with DM5 to support downstream USB port.
32 PWRON6 output Power-on/-off control signal for downstream port 6; active low, push-pull output that enables external power switch.
33 OVRCUR6 input Overcurrent input for downstream port 6; active low with noise filtering logic.
34 DM6 bidirectional USB differential data minus for downstream port 6; paired with DP6 to support downstream USB port.
35 DP6 bidirectional USB differential data plus for downstream port 6; paired with DM6 to support downstream USB port.
36 PWRON7 output Power-on/-off control signal for downstream port 7; active low, push-pull output that enables external power switch.
37 OVRCUR7 input Overcurrent input for downstream port 7; active low with noise filtering logic.
38 DM7 bidirectional USB differential data minus for downstream port 7; paired with DP7 to support downstream USB port.
39 DP7 bidirectional USB differential data plus for downstream port 7; paired with DM7 to support downstream USB port.
40 HUBCFG output Hub configured LED indicator control output; high when hub is configured (enables green LED), low when not configured (enables red LED); 3-stated during low-power suspend.
41 PORTPWR output Any port powered LED indicator control output; high when any port is powered on (enables green LED), low when all ports are off (enables red LED); 3-stated during low-power suspend.
42 PORTDIS output No ports disabled LED indicator control output; high when no port is disabled (enables green LED), low when any port is disabled (enables red LED); 3-stated during low-power suspend.
43 GND power_in Ground; must be tied to ground for proper operation.
44 XTAL2 output 6-MHz crystal oscillator output; must be left open when using an external oscillator.
45 XTAL1/CLK48 input Crystal 1/48-MHz clock input; 6-MHz crystal input with 50% duty cycle when MODE is low, 48-MHz clock input when MODE is high; internal APLL generates 48-MHz and 12-MHz clocks when MODE is low.
46 VCC power_in 3.3-V supply voltage.
47 EXTMEM input External memory enable input; when high, EEPROM interface is disabled and vendor/product IDs use defaults; when low, EECLK and EEDATA/GANGED pins are configured as EEPROM interface.
48 MODE input Mode select input; low selects APLL output clock and 6-MHz crystal input; high selects 48-MHz clock input and bypasses internal APLL.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-48(7x7)
Category Interface
Pins 48

CAD (KiCad official)

  • Symbol: TUSB2077APTR
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: tusb2077aptr-etched.step / tusb2077aptr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tusb2077aptr.step / tusb2077aptr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (29 pp, sha256 84f556408dd203b4, retrieved 2026-10-01, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF