component
TUSB2046BIRHBR
Public Made by Adomby adom
Texas Instruments USB Converters, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTUSB2046BIRHBR
Texas Instruments · USB Converters · VQFN-32-EP(5x5)
TUSB2046BIRHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DP0 | bidirectional | Root port USB differential data plus, paired with DM0 for upstream USB port, common-mode input 0.8 V to 2.5 V. |
| 2 | DM0 | bidirectional | Root port USB differential data minus, paired with DP0 for upstream USB port, common-mode input 0.8 V to 2.5 V. |
| 3 | VCC | power_in | 3.3 V supply voltage, recommended operating range 3.0 V to 3.6 V. |
| 4 | RESET | input | Active low TTL input with hysteresis; requires 100 μs to 1 ms pulse width at power-up, clock must be active during final 60 μs. |
| 5 | EECLK | output | EEPROM serial clock output with 100 μA internal pulldown when EXTMEM low, disabled when EXTMEM high. |
| 6 | EEDATA/GANGED | bidirectional | EEPROM serial data I/O with 100 μA internal pulldown when EXTMEM low, ganged mode indicator when EXTMEM high. |
| 7 | GND | power_in | Ground terminal. |
| 8 | BUSPWR | input | Active high power mode indicator; high for bus-powered or low for self-powered mode, must not change dynamically. |
| 9 | PWRON1 | output | Active low push-pull power control output for downstream port 1, 4 mA drive capability. |
| 10 | OVRCUR1 | input | Active low overcurrent input for downstream port 1 with noise filtering logic. |
| 11 | DM1 | bidirectional | Downstream port 1 USB differential data minus, paired with DP1, common-mode input 0.8 V to 2.5 V. |
| 12 | DP1 | bidirectional | Downstream port 1 USB differential data plus, paired with DM1, common-mode input 0.8 V to 2.5 V. |
| 13 | PWRON2 | output | Active low push-pull power control output for downstream port 2, 4 mA drive capability. |
| 14 | OVRCUR2 | input | Active low overcurrent input for downstream port 2 with noise filtering logic. |
| 15 | DM2 | bidirectional | Downstream port 2 USB differential data minus, paired with DP2, common-mode input 0.8 V to 2.5 V. |
| 16 | DP2 | bidirectional | Downstream port 2 USB differential data plus, paired with DM2, common-mode input 0.8 V to 2.5 V. |
| 17 | PWRON3 | output | Active low push-pull power control output for downstream port 3, 4 mA drive capability. |
| 18 | OVRCUR3 | input | Active low overcurrent input for downstream port 3 with noise filtering logic. |
| 19 | DM3 | bidirectional | Downstream port 3 USB differential data minus, paired with DP3, common-mode input 0.8 V to 2.5 V. |
| 20 | DP3 | bidirectional | Downstream port 3 USB differential data plus, paired with DP3, common-mode input 0.8 V to 2.5 V. |
| 21 | PWRON4 | output | Active low push-pull power control output for downstream port 4, 4 mA drive capability. |
| 22 | OVRCUR4 | input | Active low overcurrent input for downstream port 4 with noise filtering logic. |
| 23 | DM4 | bidirectional | Downstream port 4 USB differential data minus, paired with DP4, common-mode input 0.8 V to 2.5 V. |
| 24 | DP4 | bidirectional | Downstream port 4 USB differential data plus, paired with DP4, common-mode input 0.8 V to 2.5 V. |
| 25 | VCC | power_in | 3.3 V supply voltage, recommended operating range 3.0 V to 3.6 V. |
| 26 | EXTMEM | input | EEPROM interface control input; high disables interface, low enables pins 5-6 as serial interface, must not change during operation. |
| 27 | TSTPLL/48MCLK | bidirectional | Test terminal or 48 MHz clock input; tie to ground for 6 MHz crystal mode or connect 48 MHz clock source. |
| 28 | GND | power_in | Ground terminal. |
| 29 | XTAL2 | output | 6 MHz crystal output, must be left open when using external oscillator. |
| 30 | XTAL1 | input | 6 MHz crystal input with 50% duty cycle; internal PLL generates 48 MHz and 12 MHz clocks. |
| 31 | TSTMODE | input | Test/mode control input; tie to ground for 6 MHz or to 3.3 V for 48 MHz operation, must not change during normal operation. |
| 32 | SUSPND | output | Active high suspend status output; high during suspend mode, low during normal operation. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | Interface |
| Pins | 33 |
CAD (KiCad official)
- Symbol:
TUSB2046BIRHBR - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
tusb2046birhbr-etched.step/tusb2046birhbr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tusb2046birhbr.step/tusb2046birhbr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (33 pp, sha256
eaa20027fc3dde2d, retrieved 2026-09-24, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).