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TSZ182IYDT

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STMicroelectronics Precision OpAmps, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TSZ182IYDT

STMicroelectronics · Precision OpAmps · SO-8

TSZ182IYDT from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT1 output Output of operational amplifier channel 1, rail-to-rail.
2 IN1- input Inverting input of channel 1; input current must be limited to 10 mA by a series resistor.
3 IN1+ input Non-inverting input of channel 1, common-mode range (VCC-) - 0.1 V to (VCC+) + 0.1 V.
4 VCC- power_in Negative supply voltage (ground in single-supply use).
5 IN2+ input Non-inverting input of channel 2, common-mode range (VCC-) - 0.1 V to (VCC+) + 0.1 V.
6 IN2- input Inverting input of channel 2; input current must be limited to 10 mA by a series resistor.
7 OUT2 output Output of operational amplifier channel 2, rail-to-rail.
8 VCC+ power_in Positive supply voltage, 2.2 to 5.5 V operating (6 V absolute maximum); decouple with 0.1 µF close to the pin.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SO-8
Category Operational Amplifier/Comparator
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 6 V 3
Input current Iin 10 mA Input current must be limited by a series resistor 3
Storage temperature Tstg -65 150 °C 3
Maximum junction temperature Tj 150 °C 3
ESD HBM 4 kV Human body model 3
ESD CDM 1.5 kV Charged device model 3
Latch-up immunity 200 mA 3
Supply voltage VCC 2.2 5.5 V 3
Operating free-air temperature range Toper -40 125 °C 3
Input offset voltage Vio 3.5 35 µV VCC+ = 2.2 V; T = 25 °C 4
Input offset voltage Vio 45 µV VCC+ = 2.2 V; -40 °C < T< 125 °C 4
Input bias current Iib 30 200 pA VCC+ = 2.2 V; Vout = VCC/2; T = 25 °C 4
Input bias current Iib 300 pA VCC+ = 2.2 V; Vout = VCC/2; -40 °C < T< 125 °C 4
Input offset current Iio 60 400 pA VCC+ = 2.2 V; Vout = VCC/2; T = 25 °C 4
Common-mode rejection ratio CMR1 CMR1 96 115 dB VCC+ = 2.2 V; Vic = 0 V to VCC, Vout = VCC/2, RL > 1 MΩ; T = 25 °C 4
Large signal voltage gain Avd 112 130 VCC+ = 2.2 V; Vout = 0.5 V to (Vcc - 0.5 V); T = 25 °C 4
High-level output voltage VOH 15 40 mV VCC+ = 2.2 V; VOH = Vcc - Vout; T = 25 °C 4
Low-level output voltage VOL 10 30 mV VCC+ = 2.2 V; T = 25 °C 4
Output sink current Isink 4 6 mA VCC+ = 2.2 V; Vout = VCC; T = 25 °C 4
Output source current Isource 3.5 4 mA VCC+ = 2.2 V; Vout = 0 V; T = 25 °C 4
Supply current (per channel) ICC 0.7 1 VCC+ = 2.2 V; Vout = VCC/2, RL > 1 MΩ; T = 25 °C 4
Gain bandwidth product GBP 1.6 2.3 MHz VCC+ = 2.2 V; T = 25 °C, RL = 10 kΩ, CL = 100 pF 4
Input offset voltage Vio 2 30 µV VCC+ = 3.3 V; T = 25 °C 5
Input bias current Iib 30 200 pA VCC+ = 3.3 V; Vout = VCC/2; T = 25 °C 5
Input offset current Iio 60 400 pA VCC+ = 3.3 V; Vout = VCC/2; T = 25 °C 5
Common mode rejection ratio CMR1 CMR1 104 120 dB VCC+ = 3.3 V; Vic = 0 V to VCC, Vout = VCC/2, RL > 1 MΩ; T = 25 °C 5
Large signal voltage gain Avd 120 138 VCC+ = 3.3 V; Vout = 0.5 V to (VCC - 0.5 V); T = 25 °C 5
High-level output voltage VOH 16 40 mV VCC+ = 3.3 V; VOH = Vcc - Vout; T = 25 °C 5
Low-level output voltage VOL 11 30 mV VCC+ = 3.3 V; T = 25 °C 5
Output sink current Isink 10 15 mA VCC+ = 3.3 V; Vout = VCC; T = 25 °C 6
Supply current (per channel) ICC 0.7 1 mA VCC+ = 3.3 V; Vout = VCC/2, RL > 1 MΩ; T = 25 °C 6
Gain bandwidth product GBP 2 2.8 MHz VCC+ = 3.3 V; T = 25 °C, RL = 10 kΩ, CL = 100 pF 6
Input offset voltage Vio 1 25 µV VCC+ = 5 V; T = 25 °C 6
Input offset voltage Vio 35 µV VCC+ = 5 V; -40 °C < T< 125 °C 6
Input bias current Iib 30 200 pA VCC+ = 5 V; Vout = VCC/2; T = 25 °C 6
Input bias current Iib 300 pA VCC+ = 5 V; Vout = VCC/2; -40 °C < T< 125 °C 6
Input offset current Iio 60 400 pA VCC+ = 5 V; Vout = VCC/2; T = 25 °C 6
Input offset current Iio 600 pA VCC+ = 5 V; Vout = VCC/2; -40 °C < T< 125 °C 6
Common-mode rejection ratio CMR1 CMR1 108 126 dB VCC+ = 5 V; Vic = 0 V to VCC, Vout = VCC/2, RL > 1 MΩ; T = 25 °C 7
Common-mode rejection ratio CMR1 CMR1 108 dB VCC+ = 5 V; Vic = 0 V to VCC; -40 °C < T< 125 °C 7
Large signal voltage gain Avd 120 144 VCC+ = 5 V; Vout = 0.5 V to (Vcc - 0.5 V); T = 25 °C 7
Large signal voltage gain Avd 110 VCC+ = 5 V; Vout = 0.5 V to (Vcc - 0.5 V); -40 °C < T< 125 °C 7
High-level output voltage VOH 18 40 mV VCC+ = 5 V; VOH = Vcc - Vout; T = 25 °C 7
High-level output voltage VOH 70 mV VCC+ = 5 V; VOH = Vcc - Vout; -40 °C < T< 125 °C 7
Low-level output voltage VOL 13 30 mV VCC+ = 5 V; T = 25 °C 7
Low-level output voltage VOL 70 mV VCC+ = 5 V; -40 °C < T< 125 °C 7
Output sink current Isink 20 29 mA VCC+ = 5 V; Vout = VCC; T = 25 °C 7
Output sink current Isink 15 mA VCC+ = 5 V; Vout = VCC; -40 °C < T< 125 °C 7
Output source current Isource 15 25 mA VCC+ = 5 V; Vout = 0 V; T = 25 °C 7
Output source current Isource 10 mA VCC+ = 5 V; Vout = 0 V; -40 °C < T< 125 °C 7
Supply current (per channel) ICC 0.8 1 VCC+ = 5 V; Vout = VCC/2, RL > 1 MΩ; T = 25 °C 7
Supply current (per channel) ICC 1.2 VCC+ = 5 V; Vout = VCC/2, RL > 1 MΩ; -40 °C < T< 125 °C 7
Gain bandwidth product GBP 2 3 MHz VCC+ = 5 V; T = 25 °C, RL = 10 kΩ, CL = 100 pF 7
Gain bandwidth product GBP 1.6 MHz VCC+ = 5 V; -40 °C < T< 125 °C, RL = 10 kΩ, CL = 100 pF 7
Slew rate SR 2.9 4.7 V/µs VCC+ = 5 V; T = 25 °C 7
Slew rate SR 2.4 V/µs VCC+ = 5 V; -40 °C < T< 125 °C 7
Thermal resistance junction-to-ambient, SO8 Rthja 125 °C/W SO8 package; typical values (notes 5, 6) 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper The copper traces that connect the output pins to the load and supply pins should be as wide as possible to 21

CAD (KiCad official)

  • Symbol: TSZ182IYDT
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: tsz182iydt-etched.step / tsz182iydt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tsz182iydt.step / tsz182iydt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (43 pp, sha256 7ea4e24487017a89, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF