component
TSX7192IDT
Public Made by Adomby adom
STMicroelectronics Operational Amplifier, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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tsx7192idt: specified limits as data (metadata.characteristics, 45 rows from the datasheet)
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TSX7192IDT
STMicroelectronics · Operational Amplifier · SO-8
TSX7192IDT from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT1 | output | Output of amplifier 1, rail-to-rail, swinging to within a maximum of 40 mV of either rail with a 10 kΩ load to VCC/2. |
| 2 | IN1- | input | Inverting input of amplifier 1; input range VCC- - 0.1 V to VCC+ + 0.1 V, with input current limited to 10 mA by a series resistor. |
| 3 | IN1+ | input | Non-inverting input of amplifier 1; input range VCC- - 0.1 V to VCC+ + 0.1 V, with input current limited to 10 mA by a series resistor. |
| 4 | VCC- | power_in | Negative supply voltage (ground in single-supply use); total supply range VCC+ to VCC- is 2.7 to 16 V. |
| 5 | IN2+ | input | Non-inverting input of amplifier 2; input range VCC- - 0.1 V to VCC+ + 0.1 V, with input current limited to 10 mA by a series resistor. |
| 6 | IN2- | input | Inverting input of amplifier 2; input range VCC- - 0.1 V to VCC+ + 0.1 V, with input current limited to 10 mA by a series resistor. |
| 7 | OUT2 | output | Output of amplifier 2, rail-to-rail, swinging to within a maximum of 40 mV of either rail with a 10 kΩ load to VCC/2. |
| 8 | VCC+ | power_in | Positive supply voltage, 2.7 to 16 V operating (18 V absolute maximum); a 22 nF decoupling capacitor close to the pin is recommended. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SO-8 |
| Category | Amplifiers/Comparators |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (operating) | VCC | 2.7 | 16 | V | 4 | ||
| Operating free air temperature range | Toper | -40 | 125 | °C | 4 | ||
| Supply voltage (absolute maximum) | VCC | 18 | V | 4 | |||
| Input current | Iin | 10 | mA | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Maximum junction temperature | Tj | 150 | °C | 4 | |||
| ESD HBM (human body model) | 4000 | V | JEDEC JESD22-A114F | 4 | |||
| ESD MM (machine model) | 100 | V | JEDEC JESD22-A115A | 4 | |||
| ESD CDM (charged device model) | 1500 | V | ANSI/ESD STM5.3.1 | 4 | |||
| Latch-up immunity | 200 | mA | 4 | ||||
| Input offset voltage | Vio | 200 | μV | VCC+ = 16 V; T = 25 °C | 8 | ||
| Input offset voltage | Vio | 365 | μV | VCC+ = 16 V; Tmin < Top < 85 °C | 8 | ||
| Input offset voltage | Vio | 450 | μV | VCC+ = 16 V; Tmin < Top < 125 °C | 8 | ||
| Input offset voltage drift | ΔVio/ΔT | 2.5 | μV/°C | VCC+ = 16 V | 8 | ||
| Input bias current | Iib | 1 | 50 | pA | VCC+ = 16 V; Vout = VCC/2 | 8 | |
| Input bias current | Iib | 200 | pA | VCC+ = 16 V; Tmin < Top < Tmax | 8 | ||
| Input offset current | Iio | 1 | 50 | pA | VCC+ = 16 V; Vout = VCC/2 | 8 | |
| Input offset current | Iio | 200 | pA | VCC+ = 16 V; Tmin < Top < Tmax | 8 | ||
| Common mode rejection ratio | CMRR | 94 | 107 | dB | VCC+ = 16 V; Vicm = -0.1 to 16.1 V, Vout = VCC/2 | 8 | |
| Common mode rejection ratio | CMRR | 90 | dB | VCC+ = 16 V; Tmin < Top < Tmax; Vicm = -0.1 to 16.1 V | 8 | ||
| Common mode rejection ratio | CMRR | 100 | 107 | dB | VCC+ = 16 V; Vicm = -0.1 to 14 V, Vout = VCC/2 | 8 | |
| Supply voltage rejection ratio | SVRR | 100 | 131 | dB | VCC+ = 16 V; Vcc = 4 to 16 V | 8 | |
| Supply voltage rejection ratio | SVRR | 90 | dB | VCC+ = 16 V; Tmin < Top < Tmax; Vcc = 4 to 16 V | 8 | ||
| Large signal voltage gain | Avd | 110 | 146 | dB | VCC+ = 16 V; RL = 2 kΩ, Vout = 0.3 to 15.7 V | 8 | |
| Large signal voltage gain | Avd | 100 | dB | VCC+ = 16 V; Tmin < Top < Tmax; RL = 2 kΩ | 8 | ||
| Large signal voltage gain | Avd | 110 | 149 | dB | VCC+ = 16 V; RL = 10 kΩ, Vout = 0.2 to 15.8 V | 8 | |
| High level output voltage (voltage drop from VCC+) | VOH | 100 | 130 | mV | VCC+ = 16 V; RL = 2 kΩ | 8 | |
| High level output voltage (voltage drop from VCC+) | VOH | 150 | mV | VCC+ = 16 V; Tmin < Top < Tmax; RL = 2 kΩ | 8 | ||
| High level output voltage (voltage drop from VCC+) | VOH | 16 | 40 | mV | VCC+ = 16 V; RL = 10 kΩ | 8 | |
| High level output voltage (voltage drop from VCC+) | VOH | 50 | mV | VCC+ = 16 V; Tmin < Top < Tmax; RL = 10 kΩ | 8 | ||
| Low level output voltage | VOL | 70 | 130 | mV | VCC+ = 16 V; RL = 2 kΩ | 8 | |
| Low level output voltage | VOL | 150 | mV | VCC+ = 16 V; Tmin < Top < Tmax; RL = 2 kΩ | 8 | ||
| Low level output voltage | VOL | 15 | 40 | mV | VCC+ = 16 V; RL = 10 kΩ | 8 | |
| Low level output voltage | VOL | 50 | mV | VCC+ = 16 V; Tmin < Top < Tmax; RL = 10 kΩ | 8 | ||
| Output sink current | Isink | 30 | 40 | mA | VCC+ = 16 V; Vout = VCC | 8 | |
| Output sink current | Isink | 15 | mA | VCC+ = 16 V; Tmin < Top < Tmax; Vout = VCC | 8 | ||
| Output source current | Isource | 50 | 68 | mA | VCC+ = 16 V; Vout = 0 V | 8 | |
| Output source current | Isource | 45 | mA | VCC+ = 16 V; Tmin < Top < Tmax; Vout = 0 V | 8 | ||
| Supply current per amplifier | ICC | 660 | 900 | μA | VCC+ = 16 V; No load, Vout = VCC/2 | 8 | |
| Supply current per amplifier | ICC | 1000 | μA | VCC+ = 16 V; Tmin < Top < Tmax; No load | 8 | ||
| Gain bandwidth product | GBP | 5 | 8.5 | MHz | VCC+ = 16 V; RL = 10 kΩ, CL = 100 pF | 9 | |
| Negative slew rate | SRn | 1.5 | 2.4 | V/μs | VCC+ = 16 V; Av = 10, Vout = 10 VPP, 10 % to 90 % | 9 | |
| Negative slew rate | SRn | 1.1 | V/μs | VCC+ = 16 V; Tmin < Top < Tmax; Av = 10, Vout = 10 VPP | 9 | ||
| Positive slew rate | SRp | 1.5 | 2.5 | V/μs | VCC+ = 16 V; Av = 10, Vout = 10 VPP, 10 % to 90 % | 9 | |
| Positive slew rate | SRp | 1.1 | V/μs | VCC+ = 16 V; Tmin < Top < Tmax; Av = 10, Vout = 10 VPP | 9 |
CAD (KiCad official)
- Symbol:
TSX7192IDT - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
tsx7192idt-etched.step/tsx7192idt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tsx7192idt.step/tsx7192idt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (25 pp, sha256
e6fc1d27168a623f, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TSX7192IDT
**STMicroelectronics** · Operational Amplifier · SO-8
TSX7192IDT from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT1 | output | Output of amplifier 1, rail-to-rail, swinging to within a maximum of 40 mV of either rail with a 10 kΩ load to VCC/2. |
| 2 | IN1- | input | Inverting input of amplifier 1; input range VCC- - 0.1 V to VCC+ + 0.1 V, with input current limited to 10 mA by a series resistor. |
| 3 | IN1+ | input | Non-inverting input of amplifier 1; input range VCC- - 0.1 V to VCC+ + 0.1 V, with input current limited to 10 mA by a series resistor. |
| 4 | VCC- | power_in | Negative supply voltage (ground in single-supply use); total supply range VCC+ to VCC- is 2.7 to 16 V. |
| 5 | IN2+ | input | Non-inverting input of amplifier 2; input range VCC- - 0.1 V to VCC+ + 0.1 V, with input current limited to 10 mA by a series resistor. |
| 6 | IN2- | input | Inverting input of amplifier 2; input range VCC- - 0.1 V to VCC+ + 0.1 V, with input current limited to 10 mA by a series resistor. |
| 7 | OUT2 | output | Output of amplifier 2, rail-to-rail, swinging to within a maximum of 40 mV of either rail with a 10 kΩ load to VCC/2. |
| 8 | VCC+ | power_in | Positive supply voltage, 2.7 to 16 V operating (18 V absolute maximum); a 22 nF decoupling capacitor close to the pin is recommended. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SO-8 |
| Category | Amplifiers/Comparators |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (operating) | VCC | 2.7 | | 16 | V | | 4 |
| Operating free air temperature range | Toper | -40 | | 125 | °C | | 4 |
| Supply voltage (absolute maximum) | VCC | | | 18 | V | | 4 |
| Input current | Iin | | | 10 | mA | | 4 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 4 |
| Maximum junction temperature | Tj | | | 150 | °C | | 4 |
| ESD HBM (human body model) | | | | 4000 | V | JEDEC JESD22-A114F | 4 |
| ESD MM (machine model) | | | | 100 | V | JEDEC JESD22-A115A | 4 |
| ESD CDM (charged device model) | | | | 1500 | V | ANSI/ESD STM5.3.1 | 4 |
| Latch-up immunity | | | | 200 | mA | | 4 |
| Input offset voltage | Vio | | | 200 | μV | VCC+ = 16 V; T = 25 °C | 8 |
| Input offset voltage | Vio | | | 365 | μV | VCC+ = 16 V; Tmin < Top < 85 °C | 8 |
| Input offset voltage | Vio | | | 450 | μV | VCC+ = 16 V; Tmin < Top < 125 °C | 8 |
| Input offset voltage drift | ΔVio/ΔT | | | 2.5 | μV/°C | VCC+ = 16 V | 8 |
| Input bias current | Iib | | 1 | 50 | pA | VCC+ = 16 V; Vout = VCC/2 | 8 |
| Input bias current | Iib | | | 200 | pA | VCC+ = 16 V; Tmin < Top < Tmax | 8 |
| Input offset current | Iio | | 1 | 50 | pA | VCC+ = 16 V; Vout = VCC/2 | 8 |
| Input offset current | Iio | | | 200 | pA | VCC+ = 16 V; Tmin < Top < Tmax | 8 |
| Common mode rejection ratio | CMRR | 94 | 107 | | dB | VCC+ = 16 V; Vicm = -0.1 to 16.1 V, Vout = VCC/2 | 8 |
| Common mode rejection ratio | CMRR | 90 | | | dB | VCC+ = 16 V; Tmin < Top < Tmax; Vicm = -0.1 to 16.1 V | 8 |
| Common mode rejection ratio | CMRR | 100 | 107 | | dB | VCC+ = 16 V; Vicm = -0.1 to 14 V, Vout = VCC/2 | 8 |
| Supply voltage rejection ratio | SVRR | 100 | 131 | | dB | VCC+ = 16 V; Vcc = 4 to 16 V | 8 |
| Supply voltage rejection ratio | SVRR | 90 | | | dB | VCC+ = 16 V; Tmin < Top < Tmax; Vcc = 4 to 16 V | 8 |
| Large signal voltage gain | Avd | 110 | 146 | | dB | VCC+ = 16 V; RL = 2 kΩ, Vout = 0.3 to 15.7 V | 8 |
| Large signal voltage gain | Avd | 100 | | | dB | VCC+ = 16 V; Tmin < Top < Tmax; RL = 2 kΩ | 8 |
| Large signal voltage gain | Avd | 110 | 149 | | dB | VCC+ = 16 V; RL = 10 kΩ, Vout = 0.2 to 15.8 V | 8 |
| High level output voltage (voltage drop from VCC+) | VOH | | 100 | 130 | mV | VCC+ = 16 V; RL = 2 kΩ | 8 |
| High level output voltage (voltage drop from VCC+) | VOH | | | 150 | mV | VCC+ = 16 V; Tmin < Top < Tmax; RL = 2 kΩ | 8 |
| High level output voltage (voltage drop from VCC+) | VOH | | 16 | 40 | mV | VCC+ = 16 V; RL = 10 kΩ | 8 |
| High level output voltage (voltage drop from VCC+) | VOH | | | 50 | mV | VCC+ = 16 V; Tmin < Top < Tmax; RL = 10 kΩ | 8 |
| Low level output voltage | VOL | | 70 | 130 | mV | VCC+ = 16 V; RL = 2 kΩ | 8 |
| Low level output voltage | VOL | | | 150 | mV | VCC+ = 16 V; Tmin < Top < Tmax; RL = 2 kΩ | 8 |
| Low level output voltage | VOL | | 15 | 40 | mV | VCC+ = 16 V; RL = 10 kΩ | 8 |
| Low level output voltage | VOL | | | 50 | mV | VCC+ = 16 V; Tmin < Top < Tmax; RL = 10 kΩ | 8 |
| Output sink current | Isink | 30 | 40 | | mA | VCC+ = 16 V; Vout = VCC | 8 |
| Output sink current | Isink | 15 | | | mA | VCC+ = 16 V; Tmin < Top < Tmax; Vout = VCC | 8 |
| Output source current | Isource | 50 | 68 | | mA | VCC+ = 16 V; Vout = 0 V | 8 |
| Output source current | Isource | 45 | | | mA | VCC+ = 16 V; Tmin < Top < Tmax; Vout = 0 V | 8 |
| Supply current per amplifier | ICC | | 660 | 900 | μA | VCC+ = 16 V; No load, Vout = VCC/2 | 8 |
| Supply current per amplifier | ICC | | | 1000 | μA | VCC+ = 16 V; Tmin < Top < Tmax; No load | 8 |
| Gain bandwidth product | GBP | 5 | 8.5 | | MHz | VCC+ = 16 V; RL = 10 kΩ, CL = 100 pF | 9 |
| Negative slew rate | SRn | 1.5 | 2.4 | | V/μs | VCC+ = 16 V; Av = 10, Vout = 10 VPP, 10 % to 90 % | 9 |
| Negative slew rate | SRn | 1.1 | | | V/μs | VCC+ = 16 V; Tmin < Top < Tmax; Av = 10, Vout = 10 VPP | 9 |
| Positive slew rate | SRp | 1.5 | 2.5 | | V/μs | VCC+ = 16 V; Av = 10, Vout = 10 VPP, 10 % to 90 % | 9 |
| Positive slew rate | SRp | 1.1 | | | V/μs | VCC+ = 16 V; Tmin < Top < Tmax; Av = 10, Vout = 10 VPP | 9 |
## CAD (KiCad official)
- Symbol: `TSX7192IDT`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `tsx7192idt-etched.step` / `tsx7192idt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tsx7192idt.step` / `tsx7192idt.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589944307961524224) (25 pp, sha256 `e6fc1d27168a623f`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tsx7192idt-datasheet.pdf)