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TSV992AIST

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STMicroelectronics Operational Amplifier, MSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TSV992AIST

STMicroelectronics · Operational Amplifier · MSOP-8

TSV992AIST from STMicroelectronics, in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT1 output Channel 1 rail-to-rail output, able to source/sink about 35 mA/32 mA typ. and stable only for gain ≥ 4 or ≤ -3.
2 IN1- input Channel 1 inverting input with rail-to-rail range of (VCC-) - 0.1 V to (VCC+) + 0.1 V and 1 pA typ. bias current.
3 IN1+ input Channel 1 non-inverting input with rail-to-rail range of (VCC-) - 0.1 V to (VCC+) + 0.1 V and 1 pA typ. bias current.
4 VCC- power_in Negative supply (ground in single-supply use), reference for the 2.5 V to 5.5 V supply range.
5 IN2+ input Channel 2 non-inverting input with rail-to-rail range of (VCC-) - 0.1 V to (VCC+) + 0.1 V and 1 pA typ. bias current.
6 IN2- input Channel 2 inverting input with rail-to-rail range of (VCC-) - 0.1 V to (VCC+) + 0.1 V and 1 pA typ. bias current.
7 OUT2 output Channel 2 rail-to-rail output, able to source/sink about 35 mA/32 mA typ. and stable only for gain ≥ 4 or ≤ -3.
8 VCC+ power_in Positive supply, 2.5 V to 5.5 V operating (6 V absolute maximum), with 10 nF decoupling placed close to the pin.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package MSOP-8
Category Operational Amplifier/Comparator
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 2.5 5.5 V 3
Operating free air temperature range Top -40 125 °C 3
Offset voltage, TSV99xA Vio 1.5 mV VCC+ = 2.5 V; Top = 25 °C 4
Offset voltage, TSV99xA Vio 3 mV VCC+ = 2.5 V; Tmin < Top < Tmax 4
Input offset current Iio 1 10 pA VCC+ = 2.5 V; Vout = VCC/2; Top = 25 °C 4
Input offset current Iio 100 pA VCC+ = 2.5 V; Vout = VCC/2; Tmin < Top < Tmax 4
Input bias current Iib 1 10 pA VCC+ = 2.5 V; Vout = VCC/2; Top = 25 °C 4
Input bias current Iib 100 pA VCC+ = 2.5 V; Vout = VCC/2; Tmin < Top < Tmax 4
Common mode rejection ratio, 20 log (ΔVic/ΔVio) CMR 58 75 dB VCC+ = 2.5 V; 0 V to 2.5 V, Vout = 1.25 V, Top = 25 °C 4
Common mode rejection ratio, 20 log (ΔVic/ΔVio) CMR 53 dB VCC+ = 2.5 V; Tmin < Top < Tmax 4
Large signal voltage gain Avd 80 89 VCC+ = 2.5 V; RL = 10 kΩ, Vout = 0.5 V to 2 V, Top = 25 °C 4
Large signal voltage gain Avd 75 VCC+ = 2.5 V; Tmin < Top < Tmax 4
High-level output voltage VCC - VOH 15 40 mV VCC+ = 2.5 V; RL = 10 kΩ, Tmin < Top < Tmax 4
High-level output voltage VCC - VOH 45 150 mV VCC+ = 2.5 V; RL = 600 Ω, Tmin < Top < Tmax 4
Low-level output voltage VOL 15 40 mV VCC+ = 2.5 V; RL = 10 kΩ, Tmin < Top < Tmax 4
Low-level output voltage VOL 45 150 mV VCC+ = 2.5 V; RL = 600 Ω, Tmin < Top < Tmax 4
Output current sink Isink 18 32 mA VCC+ = 2.5 V; Vo = 2.5 V, Top = 25 °C 4
Output current sink Isink 16 mA VCC+ = 2.5 V; Tmin < Top < Tmax 4
Output current source Isource 18 35 mA VCC+ = 2.5 V; Vo = 0 V, Top = 25 °C 4
Output current source Isource 16 mA VCC+ = 2.5 V; Tmin < Top < Tmax 4
Supply current (per channel) ICC 0.78 1.1 mA VCC+ = 2.5 V; No load, Vout = VCC/2, Tmin < Top < Tmax 4
Offset voltage, TSV99xA Vio 1.5 mV VCC+ = 3.3 V; Top = 25 °C 5
Offset voltage, TSV99xA Vio 3 mV VCC+ = 3.3 V; Tmin < Top < Tmax 5
Input offset current Iio 1 10 pA VCC+ = 3.3 V; Vout = VCC/2; Top = 25 °C 5
Input offset current Iio 100 pA VCC+ = 3.3 V; Vout = VCC/2; Tmin < Top < Tmax 5
Input bias current Iib 1 10 pA VCC+ = 3.3 V; Vout = VCC/2; Top = 25 °C 5
Input bias current Iib 100 pA VCC+ = 3.3 V; Vout = VCC/2; Tmin < Top < Tmax 5
Common mode rejection ratio, 20 log (ΔVic/ΔVio) CMR 60 78 dB VCC+ = 3.3 V; 0 V to 3.3 V, Vout = 1.65 V, Top = 25 °C 5
Common mode rejection ratio, 20 log (ΔVic/ΔVio) CMR 55 dB VCC+ = 3.3 V; Tmin < Top < Tmax 5
Large signal voltage gain Avd 80 89 VCC+ = 3.3 V; RL = 10 kΩ, Vout = 0.5 V to 2.8 V, Top = 25 °C 5
Large signal voltage gain Avd 75 VCC+ = 3.3 V; Tmin < Top < Tmax 5
High-level output voltage VCC - VOH 15 40 mV VCC+ = 3.3 V; RL = 10 kΩ, Tmin < Top < Tmax 5
High-level output voltage VCC - VOH 45 150 mV VCC+ = 3.3 V; RL = 600 Ω, Tmin < Top < Tmax 5
Low-level output voltage VOL 15 40 mV VCC+ = 3.3 V; RL = 10 kΩ, Tmin < Top < Tmax 5
Low-level output voltage VOL 45 150 mV VCC+ = 3.3 V; RL = 600 Ω, Tmin < Top < Tmax 5
Output current sink Isink 18 32 mA VCC+ = 3.3 V; Vo = 3.3 V, Top = 25 °C 5
Output current sink Isink 16 mA VCC+ = 3.3 V; Tmin < Top < Tmax 5
Output current source Isource 18 35 mA VCC+ = 3.3 V; Vo = 0 V, Top = 25 °C 5
Output current source Isource 16 mA VCC+ = 3.3 V; Tmin < Top < Tmax 5
Supply current (per channel) ICC 0.8 1.1 mA VCC+ = 3.3 V; No load, Vout = VCC/2, Tmin < Top < Tmax 5
Offset voltage, TSV99xA Vio 1.5 mV VCC+ = 5 V; Top = 25 °C 6
Offset voltage, TSV99xA Vio 3 mV VCC+ = 5 V; Tmin < Top < Tmax 6
Input offset current Iio 1 10 pA VCC+ = 5 V; Vout = VCC/2; Top = 25 °C 6
Input offset current Iio 100 pA VCC+ = 5 V; Vout = VCC/2; Tmin < Top < Tmax 6
Input bias current Iib 1 10 pA VCC+ = 5 V; Vout = VCC/2; Top = 25 °C 6
Input bias current Iib 100 pA VCC+ = 5 V; Vout = VCC/2; Tmin < Top < Tmax 6
Common mode rejection ratio, 20 log (ΔVic/ΔVio) CMR 62 82 dB VCC+ = 5 V; 0 V to 5 V, Vout = 2.5 V, Top = 25 °C 6
Common mode rejection ratio, 20 log (ΔVic/ΔVio) CMR 57 dB VCC+ = 5 V; Tmin < Top < Tmax 6
Supply voltage rejection ratio, 20 log (ΔVcc/ΔVio) SVR 70 86 VCC = 2.5 V to 5 V 6
Large signal voltage gain Avd 80 91 VCC+ = 5 V; RL = 10 kΩ, Vout = 0.5 V to 4.5 V, Top = 25 °C 6
Large signal voltage gain Avd 75 VCC+ = 5 V; Tmin < Top < Tmax 6
High-level output voltage VCC - VOH 15 40 mV VCC+ = 5 V; RL = 10 kΩ, Tmin < Top < Tmax 6
High-level output voltage VCC - VOH 45 150 mV VCC+ = 5 V; RL = 600 Ω, Tmin < Top < Tmax 6
Low-level output voltage VOL 15 40 mV VCC+ = 5 V; RL = 10 kΩ, Tmin < Top < Tmax 6
Low-level output voltage VOL 45 150 mV VCC+ = 5 V; RL = 600 Ω, Tmin < Top < Tmax 6
Output current sink Isink 18 32 mA VCC+ = 5 V; Vo = 5 V, Top = 25 °C 7
Output current sink Isink 16 mA VCC+ = 5 V; Tmin < Top < Tmax 7
Output current source Isource 18 35 mA VCC+ = 5 V; Vo = 0 V, Top = 25 °C 7
Output current source Isource 16 mA VCC+ = 5 V; Tmin < Top < Tmax 7
Supply current (per channel) ICC 0.82 1.1 mA VCC+ = 5 V; No load, Vout = 2.5 V, Tmin < Top < Tmax 7

CAD (KiCad official)

  • Symbol: TSV992AIST
  • Footprint: Package_SO:MSOP-8_3x3mm_P0.65mm
  • 3D model: MSOP-8 (KiCad packages3D, STEP)
  • 3D model files: tsv992aist-etched.step / tsv992aist-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tsv992aist.step / tsv992aist.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (28 pp, sha256 63a00583e4419e0b, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF