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TSV991AIQ2T

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STMicroelectronics Operational Amplifier, DFN-8-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TSV991AIQ2T

STMicroelectronics · Operational Amplifier · DFN-8-EP(2x2)

TSV991AIQ2T from STMicroelectronics, in a DFN-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN- input Inverting input; input current must be limited by a series resistor to 10 mA max and the common-mode range is (VCC-) - 0.1 V to (VCC+) + 0.1 V.
2 IN+ input Non-inverting input; input current must be limited by a series resistor to 10 mA max and the common-mode range is (VCC-) - 0.1 V to (VCC+) + 0.1 V.
3 VCC- power_in Negative supply (ground for single-supply use); the supply voltage VCC is 2.5 V to 5.5 V with respect to this pin.
4 NC unconnected No connect pin with no internal connection stated.
5 NC unconnected No connect pin with no internal connection stated.
6 OUT output Rail-to-rail amplifier output sourcing/sinking about 35 mA, stable for gain of 4 or more or -3 or less.
7 VCC- power_in Negative supply, shown as a second VCC- pin on the DFN8 pinout; supply range is 2.5 V to 5.5 V, with 10 nF decoupling advised close to the supply pins.
8 VCC+ power_in Positive supply, 2.5 V to 5.5 V (absolute maximum 6 V) with respect to VCC-, with 10 nF decoupling advised close to the pin.
9 EP unconnected Exposed pad is not internally connected and can be set to ground or left floating.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package DFN-8-EP(2x2)
Category Amplifiers/Comparators
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input offset voltage, TSV99xA, Top = 25 °C Vio 1.5 mV Top = 25 °C 4
Input offset voltage, TSV99xA, full temperature range Vio 3 mV Tmin < Top < Tmax 4
Input offset current Iio 1 10 pA Vout = VCC/2, Top = 25 °C 4
Input offset current, full temperature range Iio 100 pA Vout = VCC/2, Tmin < Top < Tmax 4
Input bias current Iib 1 10 pA Vout = VCC/2, Top = 25 °C 4
Input bias current, full temperature range Iib 100 pA Vout = VCC/2, Tmin < Top < Tmax 4
VCC - VOH high-level output voltage, RL = 10 kΩ VCC - VOH 15 40 mV RL = 10 kΩ, Tmin < Top < Tmax 4
VCC - VOH high-level output voltage, RL = 600 Ω VCC - VOH 45 150 mV RL = 600 Ω, Tmin < Top < Tmax 4
VOL low-level output voltage, RL = 10 kΩ VOL 15 40 mV RL = 10 kΩ, Tmin < Top < Tmax 4
VOL low-level output voltage, RL = 600 Ω VOL 45 150 mV RL = 600 Ω, Tmin < Top < Tmax 4
Minimum gain for stability, positive gain configuration Gain 4 V/V Phase margin = 45 °, Rf = 10 kΩ, RL = 2 kΩ, CL = 100 pF, Top = 25 °C, positive gain configuration 4
Minimum gain for stability, negative gain configuration Gain -3 V/V Phase margin = 45 °, Rf = 10 kΩ, RL = 2 kΩ, CL = 100 pF, Top = 25 °C, negative gain configuration 5
Slew rate SR 10 V/μs RL = 2 kΩ, CL = 100 pF, Top = 25 °C 5
Common mode rejection ratio, VCC+ = 2.5 V CMR 58 75 dB VCC+ = 2.5 V; 0 V to 2.5 V, Vout = 1.25 V, Top = 25 °C 4
Common mode rejection ratio, VCC+ = 2.5 V, full temperature range CMR 53 dB VCC+ = 2.5 V; Tmin < Top < Tmax 4
Large signal voltage gain, VCC+ = 2.5 V Avd 80 89 dB VCC+ = 2.5 V; RL = 10 kΩ, Vout = 0.5 V to 2 V, Top = 25 °C 4
Large signal voltage gain, VCC+ = 2.5 V, full temperature range Avd 75 dB VCC+ = 2.5 V; RL = 10 kΩ, Vout = 0.5 V to 2 V, Tmin < Top < Tmax 4
Output sink current, VCC+ = 2.5 V Isink 18 32 mA VCC+ = 2.5 V; Vo = 2.5 V, Top = 25 °C 4
Output sink current, VCC+ = 2.5 V, full temperature range Isink 16 mA VCC+ = 2.5 V; Vo = 2.5 V, Tmin < Top < Tmax 4
Output source current, VCC+ = 2.5 V Isource 18 35 mA VCC+ = 2.5 V; Vo = 0 V, Top = 25 °C 4
Output source current, VCC+ = 2.5 V, full temperature range Isource 16 mA VCC+ = 2.5 V; Vo = 0 V, Tmin < Top < Tmax 4
Supply current (per channel), VCC+ = 2.5 V ICC 0.78 1.1 mA VCC+ = 2.5 V; No load, Vout = VCC/2, Tmin < Top < Tmax 4
Common mode rejection ratio, VCC+ = 3.3 V CMR 60 78 dB VCC+ = 3.3 V; 0 V to 3.3 V, Vout = 1.65 V, Top = 25 °C 5
Common mode rejection ratio, VCC+ = 3.3 V, full temperature range CMR 55 dB VCC+ = 3.3 V; Tmin < Top < Tmax 5
Large signal voltage gain, VCC+ = 3.3 V Avd 80 89 dB VCC+ = 3.3 V; RL = 10 kΩ, Vout = 0.5 V to 2.8 V, Top = 25 °C 5
Large signal voltage gain, VCC+ = 3.3 V, full temperature range Avd 75 dB VCC+ = 3.3 V; RL = 10 kΩ, Vout = 0.5 V to 2.8 V, Tmin < Top < Tmax 5
Output sink current, VCC+ = 3.3 V Isink 18 32 mA VCC+ = 3.3 V; Vo = 3.3 V, Top = 25 °C 5
Output sink current, VCC+ = 3.3 V, full temperature range Isink 16 mA VCC+ = 3.3 V; Vo = 3.3 V, Tmin < Top < Tmax 5
Output source current, VCC+ = 3.3 V Isource 18 35 mA VCC+ = 3.3 V; Vo = 0 V, Top = 25 °C 5
Output source current, VCC+ = 3.3 V, full temperature range Isource 16 mA VCC+ = 3.3 V; Vo = 0 V, Tmin < Top < Tmax 5
Supply current (per channel), VCC+ = 3.3 V ICC 0.8 1.1 mA VCC+ = 3.3 V; No load, Vout = VCC/2, Tmin < Top < Tmax 5
Common mode rejection ratio, VCC+ = 5 V CMR 62 82 dB VCC+ = 5 V; 0 V to 5 V, Vout = 2.5 V, Top = 25 °C 6
Common mode rejection ratio, VCC+ = 5 V, full temperature range CMR 57 dB VCC+ = 5 V; Tmin < Top < Tmax 6
Supply voltage rejection ratio SVR 70 86 dB VCC+ = 5 V; VCC = 2.5 V to 5 V 6
Large signal voltage gain, VCC+ = 5 V Avd 80 91 dB VCC+ = 5 V; RL = 10 kΩ, Vout = 0.5 V to 4.5 V, Top = 25 °C 6
Large signal voltage gain, VCC+ = 5 V, full temperature range Avd 75 dB VCC+ = 5 V; RL = 10 kΩ, Vout = 0.5 V to 4.5 V, Tmin < Top < Tmax 6
Output sink current, VCC+ = 5 V Isink 18 32 mA VCC+ = 5 V; Vo = 5 V, Top = 25 °C 7
Output sink current, VCC+ = 5 V, full temperature range Isink 16 mA VCC+ = 5 V; Vo = 5 V, Tmin < Top < Tmax 7
Output source current, VCC+ = 5 V Isource 18 35 mA VCC+ = 5 V; Vo = 0 V, Top = 25 °C 7
Output source current, VCC+ = 5 V, full temperature range Isource 16 mA VCC+ = 5 V; Vo = 0 V, Tmin < Top < Tmax 7
Supply current (per channel), VCC+ = 5 V ICC 0.82 1.1 mA VCC+ = 5 V; No load, Vout = 2.5 V, Tmin < Top < Tmax 7
Supply voltage (VCC) VCC 6 V Value is with respect to the VCC- pin 2
Input current Iin 10 mA Input current must be limited by a resistor in series with the inputs 2
Storage temperature Tstg -65 150 °C 2
Maximum junction temperature Tj 150 °C 2
Thermal resistance junction to ambient, DFN8 2x2 Rthja 57 °C/W DFN8 2x2 package; Rth are typical values 2
ESD human body model (HBM) 5 kV Human body model 2
ESD machine model (MM) 400 V Machine model 2
ESD charged device model (CDM), DFN8 2x2 1500 V Charged device model, DFN8 2x2 2
Latch-up immunity 200 mA 2
Supply voltage VCC 2.5 5.5 V 3
Operating free air temperature range Top -40 125 °C 3

CAD (KiCad official)

  • Symbol: TSV991AIQ2T
  • Footprint: Package_DFN_QFN:DFN-8-1EP_2x2mm_P0.5mm_EP0.6x1.2mm
  • 3D model: DFN-8-EP(2x2) (KiCad packages3D, STEP)
  • 3D model files: tsv991aiq2t-etched.step / tsv991aiq2t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tsv991aiq2t.step / tsv991aiq2t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (28 pp, sha256 63a00583e4419e0b, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF