Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

TSV7722IDT

STMicroelectronics · Operational Amplifier · SO-8

TSV7722IDT from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT1 output Output channel 1 of the dual amplifier; the output swings rail-to-rail.
2 IN1- input Inverting input channel 1; common-mode input range is VCC- - 0.1 V to VCC+ - 1.1 V (Table 5).
3 IN1+ input Non-inverting input channel 1; common-mode input range is VCC- - 0.1 V to VCC+ - 1.1 V (Table 5).
4 VCC- power_in Negative supply voltage; all absolute maximum voltages are referenced to this pin, and the supply runs from 1.8 V to 5.5 V (Table 5).
5 IN2+ input Non-inverting input channel 2; common-mode input range is VCC- - 0.1 V to VCC+ - 1.1 V (Table 5).
6 IN2- input Inverting input channel 2; common-mode input range is VCC- - 0.1 V to VCC+ - 1.1 V (Table 5).
7 OUT2 output Output channel 2 of the dual amplifier; the output swings rail-to-rail.
8 VCC+ power_in Positive supply voltage; the supply runs from 1.8 V to 5.5 V relative to VCC- (Table 5).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SO-8
Category Operational Amplifier/Comparator
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (referred to VCC- pin) VCC -0.3 6 V 5
Input pins input current IIN -10 10 mA 5
Storage temperature Tstg -65 150 °C 5
Maximum junction temperature Tj 150 °C 5
Supply voltage VCC 1.8 5.5 V 5
Operating free air temperature range Toper -40 125 °C 5
Input offset voltage Vio -250 50 250 µV T = 25°C, Vicm = 0 V 6
Input offset voltage Vio -650 650 µV -40°C < T < 125°C, Vicm = 0 V 6
Input offset voltage drift ∆Vio/∆T -4 4 4 µV/°C -40°C < T < 125°C, Vicm = 0 V 6
Input bias current Iib 75 pA -40°C < T < 125°C, VOUT = VCC/2 6
Input offset current Iio 20 pA -40°C < T < 125°C, VOUT = VCC/2 6
Common-mode rejection ratio 1 CMR1 76 99 dB T = 25°C, Vicm = 0 V to VCC- 1.1 V, RL > 1 MΩ 6
Common-mode rejection ratio 1 CMR1 74 dB -40°C < T < 125°C, Vicm = 0 V to VCC- 1.1 V, RL > 1 MΩ 6
Common-mode rejection ratio 2 CMR2 75 dB T = 25°C, Vicm = -0.1 V to VCC- 1.1 V, RL > 1 MΩ 6
Common-mode rejection ratio 2 CMR2 60 dB -40°C < T < 125°C, Vicm = -0.1 V to VCC- 1.1 V, RL > 1 MΩ 6
Supply voltage rejection ratio SVR 85 108 dB T = 25°C, VCC = 1.8 V to 5.5 V, Vicm = 0 V, RL > 1 MΩ 6
Supply voltage rejection ratio SVR 80 dB -40°C < T < 125°C, VCC = 1.8 V to 5.5 V, Vicm = 0 V, RL > 1 MΩ 6
Large signal voltage gain AVD 111 130 dB T = 25°C, VOUT = 0.3 V to (VCC- 0.3 V) 6
Large signal voltage gain AVD 106 dB -40°C < T < 125°C, VOUT = 0.3 V to (VCC- 0.3 V) 6
High level output voltage VOH 25 mV -40°C < T < 125°C, VOH = VCC - VOUT 6
Low level output voltage VOL 25 mV -40°C < T < 125°C 6
Output source/sink current Isink IOUT 50 70 mA T = 25°C, Isink (VOUT = VCC) 6
Output source/sink current Isink IOUT 45 mA -40°C < T < 125°C, Isink (VOUT = VCC) 6
Output source current Isource IOUT 45 65 mA T = 25°C, Isource (VOUT = 0 V) 6
Output source current Isource IOUT 40 mA -40°C < T < 125°C, Isource (VOUT = 0 V) 6
Supply current (per channel) ICC 1.7 2.2 mA T = 25°C, VOUT = VCC/2, RL > 1 MΩ 6
Supply current (per channel) ICC 2.5 mA -40°C < T < 125°C, VOUT = VCC/2, RL > 1 MΩ 6
Gain bandwidth product GBW 15 22 MHz CL = 47 pF 6
Slew rate SR 8 11 V/µs 6
Input offset voltage (3.3 V) Vio -200 50 200 µV T = 25°C, Vicm = 0 V, VCC+ = 3.3 V 8
Input offset voltage (3.3 V) Vio -600 600 µV -40°C < T < 125°C, Vicm = 0 V, VCC+ = 3.3 V 8
Supply current per channel (3.3 V) ICC 1.7 2.2 mA T = 25°C, VOUT = VCC/2, RL > 1 MΩ, VCC+ = 3.3 V 8
Supply current per channel (3.3 V) ICC 2.5 mA -40°C < T < 125°C, VOUT = VCC/2, RL > 1 MΩ, VCC+ = 3.3 V 8
Gain bandwidth product (3.3 V) GBW 14 21 MHz CL = 47 pF, VCC+ = 3.3 V 8
Slew rate (3.3 V) SR 7.7 11 V/µs VCC+ = 3.3 V 8
Output source/sink current Isink (3.3 V) IOUT 50 70 mA T = 25°C, Isink (VOUT = VCC), VCC+ = 3.3 V 8
Output source current Isource (3.3 V) IOUT 45 65 mA T = 25°C, Isource (VOUT = 0 V), VCC+ = 3.3 V 8
Common-mode rejection ratio 1 (3.3 V) CMR1 75 96 dB T = 25°C, Vicm = 0 V to VCC- 1.1 V, RL > 1 MΩ, VCC+ = 3.3 V 8
Large signal voltage gain (3.3 V) AVD 107 128 dB T = 25°C, VOUT = 0.3 V to (VCC- 0.3 V), VCC+ = 3.3 V 8
Input offset voltage (1.8 V) Vio -250 50 250 µV T = 25°C, Vicm = 0 V, VCC+ = 1.8 V 10
Input offset voltage (1.8 V) Vio -650 650 µV -40°C < T < 125°C, Vicm = 0 V, VCC+ = 1.8 V 10
Supply current per channel (1.8 V) ICC 1.7 2.2 mA T = 25°C, VOUT = VCC/2, RL > 1 MΩ, VCC+ = 1.8 V 10
Supply current per channel (1.8 V) ICC 2.5 mA -40°C < T < 125°C, VOUT = VCC/2, RL > 1 MΩ, VCC+ = 1.8 V 10
Gain bandwidth product (1.8 V) GBW 14 21 MHz CL = 47 pF, VCC+ = 1.8 V 10
Slew rate (1.8 V) SR 7.6 11 V/µs VCC+ = 1.8 V 10
Output source/sink current Isink (1.8 V) IOUT 35 42 mA T = 25°C, Isink (VOUT = VCC), VCC+ = 1.8 V 10
Output source current Isource (1.8 V) IOUT 20 32 mA T = 25°C, Isource (VOUT = 0 V), VCC+ = 1.8 V 10
Common-mode rejection ratio 1 (1.8 V) CMR1 72 93 dB T = 25°C, Vicm = 0 V to VCC- 1.1 V, RL > 1 MΩ, VCC+ = 1.8 V 10
Large signal voltage gain (1.8 V) AVD 101 122 dB T = 25°C, VOUT = 0.3 V to (VCC- 0.3 V), VCC+ = 1.8 V 10
Thermal resistance junction-to-ambient (SO8) Rth-ja 113 °C / W SO8 package; typical value 5

CAD (KiCad official)

  • Symbol: TSV7722IDT
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: tsv7722idt-etched.step / tsv7722idt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tsv7722idt.step / tsv7722idt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (39 pp, sha256 fdffb4942cba98bc, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF