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TSS521DR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SOIC-16

TSS521DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BUSL2 passive Meter-Bus connection, polarity independent through the input rectifier bridge BR; bus voltage is 10.8 V to 42 V for the receiver and 12 V to 42 V for the transmitter.
2 VB power_in Differential bus voltage after the rectifier, referenced to GND and monitored by comparator TC2 for power fail; the rectifier drop ΔVBR is 1.5 V max at IBUS = 3 mA.
3 STC passive Support capacitor pin where storage capacitor CSTC is charged by a constant current and limited to REF1; the VDD turn-on and turn-off thresholds are monitored here.
4 RIDD passive Current adjustment input; resistor RRIDD sets the STC charge current, with 13 kΩ to 80 kΩ recommended and VRIDD of 1.23 V to 1.33 V at RRIDD = 30 kΩ.
5 PF output Power-fail output that is high when VVB > VSTC + 0.6 V and goes low (power fail) to warn the microcontroller of a critical voltage drop so it can save data immediately.
6 SC passive Sampling capacitor pin that provides the dynamic reference level for comparator TC3, with a charge current of −15 µA to −40 µA.
7 TXI output Inverted data output; VOH is at least VBAT − 0.6 V at −100 µA and VOL is 0.5 V max at 100 µA.
8 TX output Noninverted data output that also repeats the receiver modulation as ECHO; VOH is at least VBAT − 0.6 V at −100 µA and VOL is 0.5 V max at 100 µA.
9 BAT power_in Logic level adjust input supplied from the battery, with 2.5 V to 3.8 V recommended and VBAT(max) ≤ VSTC − 1 V.
10 VS power_out Switch output for bus or battery supply, synchronized with VDD; VVS is at least VSTC − 0.4 V at IVS = −5 µA when VDD is on, and it drives an external transistor (BSS84) to switch to battery.
11 VDD power_out Voltage regulator output at 3.3 V nominal; VVDD is 3.1 V to 3.4 V at −IVDD = 1 mA with VSTC = 6.5 V.
12 RX input Noninverted data input that controls the slave-to-master current source CS3; VIH is up to 5.5 V only when VSTC ≥ 6.5 V and VIL is 0.8 V max.
13 RXI input Inverted data input that controls the slave-to-master current source CS3; VIH is up to 5.5 V only when VSTC ≥ 6.5 V and VIL is 0.8 V max.
14 RIS passive Adjust input for modulation current; programming resistor RRIS of at least 100 Ω sets the current, with VRIS of 1.4 V to 1.7 V at 100 Ω.
15 GND power_in Ground reference; all voltage values in the datasheet are measured with respect to this terminal.
16 BUSL1 passive Meter-Bus connection, polarity independent through the input rectifier bridge BR; bus voltage is 10.8 V to 42 V for the receiver and 12 V to 42 V for the transmitter.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: TSS521DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: tss521dr-etched.step / tss521dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tss521dr.step / tss521dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (15 pp, sha256 fa7ed42a397edb3a, retrieved 2026-10-08, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF