component

TSH82IYDT

Public Made by Adom

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STMicroelectronics Operational Amplifier, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentamplifiers-comparatorstsh82iydtfactory-2.0.0extractor-text

Verified TSH82IYDT

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TSH82IYDT · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 30-page datasheet
  • ✓distributor: lcsc C2971496, digikey 497-10276-2-ND, mouser 511-TSH82IYDT
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-dcoj7psy/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.25)
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tsh82iydt.kicad_sym✓ tsh82iydt.kicad_mod✓ tsh82iydt.step
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Ray Publish 0.1.0 8a83445 4h ago

TSH82IYDT

STMicroelectronics · Operational Amplifier · SOIC-8

TSH82IYDT from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Output1 output Output of operational amplifier 1, rail-to-rail, able to drive 150 Ω loads with up to 55 mA.
2 Inverting input1 input Inverting input of operational amplifier 1.
3 Non-inv. input1 input Non-inverting input of operational amplifier 1, common mode range VCC- to (VCC+ - 1.1) V.
4 VCC- power_in Negative supply voltage, or ground in single-supply operation; total supply 4.5 to 12 V.
5 Non-inv. input2 input Non-inverting input of operational amplifier 2, common mode range VCC- to (VCC+ - 1.1) V.
6 Inverting input2 input Inverting input of operational amplifier 2.
7 Output2 output Output of operational amplifier 2, rail-to-rail, able to drive 150 Ω loads with up to 55 mA.
8 VCC+ power_in Positive supply voltage; total supply 4.5 to 12 V, absolute maximum 14 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SOIC-8
Category Amplifiers/Comparators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (absolute maximum) VCC 14 V 6
Differential input voltage Vid -2 2 V Non-inverting input with respect to inverting input 6
Input voltage Vi -6 6 V Magnitude must never exceed VCC+ +0.3 V 6
Operating free air temperature range Toper -40 85 °C 6
Storage temperature Tstg -65 150 °C 6
Maximum junction temperature Tj 150 °C 6
ESD human body model HBM 2 kV Human body model 6
ESD machine model MM 0.2 kV Machine model 6
ESD charged device model CDM 1.5 kV Charged device model 6
Thermal resistance junction-to-case (SO8) Rthjc 28 °C/W SO8 package column 6
Thermal resistance junction-to-ambient area (SO8) Rthja 157 °C/W SO8 package column 6
Supply voltage (operating) VCC 4.5 12 V 6
Input offset voltage /Vio/ 1.1 10 mV Tamb = 25 °C, VCC+ = +5 V, VCC- = GND, Vic = 2.5 V 7
Input offset voltage /Vio/ 12 mV Tmin < Tamb < Tmax, VCC+ = +5 V, VCC- = GND, Vic = 2.5 V 7
Input offset current Iio 0.1 3.5 µA Tamb = 25 °C, VCC+ = +5 V, VCC- = GND, Vic = 2.5 V 7
Input offset current Iio 5 µA Tmin < Tamb < Tmax, VCC+ = +5 V, VCC- = GND, Vic = 2.5 V 7
Input bias current Iib 6 15 Tamb = 25 °C, VCC+ = +5 V, VCC- = GND, Vic = 2.5 V 7
Input bias current Iib 20 Tmin < Tamb < Tmax, VCC+ = +5 V, VCC- = GND, Vic = 2.5 V 7
Supply current per operator ICC 8.2 10.5 mA Tamb = 25 °C, VCC+ = +5 V, VCC- = GND 7
Supply current per operator ICC 11.5 mA Tmin < Tamb < Tmax, VCC+ = +5 V, VCC- = GND 7
Common mode rejection ratio (ΔVic/ΔVio) CMR 72 97 dB +0.1< Vic< 3.9 V and Vout = 2.5 V, Tamb = 25 °C 7
Common mode rejection ratio (ΔVic/ΔVio) CMR 70 dB +0.1< Vic< 3.9 V and Vout = 2.5 V, Tmin < Tamb < Tmax 7
Supply voltage rejection ratio (ΔVCC/ΔVio) SVR 68 75 Tamb = 25 °C 7
Supply voltage rejection ratio (ΔVCC/ΔVio) SVR 65 Tmin < Tamb < Tmax 7
Large signal voltage gain Avd 75 84 RL = 150 Ω connected to 1.5 V and Vout = 1 V to 4 V, Tamb = 25 °C 7
Large signal voltage gain Avd 70 RL = 150 Ω connected to 1.5 V and Vout = 1 V to 4 V, Tmin < Tamb < Tmax 7
Output current /Source/ Io /Source/ 35 55 mA Vid = +1, Vout connected to 1.5 V, Tamb = 25 °C 7
Output current /Source/ Io /Source/ 28 mA Vid = +1, Vout connected to 1.5 V, Tmin < Tamb < Tmax 7
Output current Sink Io Sink 33 55 mA Vid = -1, Vout connected to 1.5 V, Tamb = 25 °C 7
Output current Sink Io Sink 28 mA Vid = -1, Vout connected to 1.5 V, Tmin < Tamb < Tmax 7
Input offset voltage /Vio/ 0.8 10 mV Tamb = 25 °C, VCC+ = +5 V, VCC- = -5 V, Vic = GND 10
Input offset voltage /Vio/ 12 mV Tmin < Tamb < Tmax, VCC+ = +5 V, VCC- = -5 V, Vic = GND 10
Input offset current Iio 0.1 3.5 µA Tamb = 25 °C, VCC+ = +5 V, VCC- = -5 V, Vic = GND 10
Input offset current Iio 5 µA Tmin < Tamb < Tmax, VCC+ = +5 V, VCC- = -5 V, Vic = GND 10
Input bias current Iib 6 15 Tamb = 25 °C, VCC+ = +5 V, VCC- = -5 V, Vic = GND 10
Input bias current Iib 20 Tmin < Tamb < Tmax, VCC+ = +5 V, VCC- = -5 V, Vic = GND 10
Supply current per operator ICC 9.8 12.3 mA Tamb = 25 °C, VCC+ = +5 V, VCC- = -5 V, Vic = GND 10
Supply current per operator ICC 13.4 mA Tmin < Tamb < Tmax, VCC+ = +5 V, VCC- = -5 V, Vic = GND 10
Common mode rejection ratio (ΔVic/ΔVio) CMR 81 106 dB -4.9 < Vic < 3.9 V and Vout = GND, Tamb = 25 °C 10
Common mode rejection ratio (ΔVic/ΔVio) CMR 72 dB -4.9 < Vic < 3.9 V and Vout = GND, Tmin < Tamb < Tmax 10
Supply voltage rejection ratio (ΔVCC/ΔVio) SVR 71 77 Tamb = 25 °C 10
Supply voltage rejection ratio (ΔVCC/ΔVio) SVR 65 Tmin < Tamb < Tmax 10
Large signal voltage gain Avd 75 86 RL = 150 Ω connected to GND and Vout = -4 to +4, Tamb = 25 °C 10
Large signal voltage gain Avd 70 RL = 150 Ω connected to GND and Vout = -4 to +4, Tmin < Tamb < Tmax 10
Output current /Source/ Io /Source/ 35 55 mA Vid = +1, Vout connected to 1.5 V, Tamb = 25 °C 10
Output current /Source/ Io /Source/ 28 mA Vid = +1, Vout connected to 1.5 V, Tmin < Tamb < Tmax 10
Output current Sink Io Sink 30 55 mA Vid = -1, Vout connected to 1.5 V, Tamb = 25 °C 10
Output current Sink Io Sink 28 mA Vid = -1, Vout connected to 1.5 V, Tmin < Tamb < Tmax 10

CAD (KiCad official)

  • Symbol: TSH82IYDT
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tsh82iydt-etched.step / tsh82iydt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tsh82iydt.step / tsh82iydt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (30 pp, sha256 78661ee32fe192fb, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF