TSER953RHBT from Texas Instruments, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CSI_D1P	input	DPHY CSI-2 data input pin; connect to a CSI-2 data source with matched 100-Ω (±5%) impedance interconnects, and it may be left floating if unused.
2	CSI_D1N	input	DPHY CSI-2 data input pin; connect to a CSI-2 data source with matched 100-Ω (±5%) impedance interconnects, and it may be left floating if unused.
3	CSI_D0P	input	DPHY CSI-2 data input pin; connect to a CSI-2 data source with matched 100-Ω (±5%) impedance interconnects, and it may be left floating if unused.
4	CSI_D0N	input	DPHY CSI-2 data input pin; connect to a CSI-2 data source with matched 100-Ω (±5%) impedance interconnects, and it may be left floating if unused.
5	CSI_CLKP	input	DPHY CSI-2 clock input pin; connect to a CSI-2 clock source with matched 100-Ω (±5%) impedance interconnects.
6	CSI_CLKN	input	DPHY CSI-2 clock input pin; connect to a CSI-2 clock source with matched 100-Ω (±5%) impedance interconnects.
7	RES0	input	Reserved pin that must be connected to GND.
8	PDB	input	Power-down inverted input with internal 1-MΩ pulldown; 1.8 V enables the device and 0 powers it down, and the input is not 3.3-V tolerant.
9	LPF1	passive	Loop filter 1 pin; connect as described in Section 8.2.2.4.
10	VDDPLL_CAP	power_out	Connection for an internal analog regulator decoupling capacitor, typically 10-µF, 0.1-µF and 0.01-µF to GND; do not connect to an external supply rail.
11	VDDPLL	power_in	1.8-V (±5%) analog power supply pin for the PLL, typically decoupled with 1-µF and 0.01-µF capacitors to GND.
12	LPF2	passive	Loop filter 2 pin; connect as described in Section 8.2.2.4.
13	DOUT-	bidirectional	V3Link differential input/output pin that must be AC-coupled; see Table 8-3 for recommended capacitor values.
14	DOUT+	bidirectional	V3Link differential input/output pin that must be AC-coupled; see Table 8-3 for recommended capacitor values.
15	VDDDRV_CAP	power_out	Connection for an internal analog regulator decoupling capacitor, typically 10-µF, 0.1-µF and 0.01-µF to GND; do not connect to an external supply rail.
16	VDDDRV	power_in	1.8-V (±5%) analog power supply pin, typically decoupled with 1-µF and 0.01-µF capacitors to GND.
17	GPIO_0	bidirectional	General-purpose input/output pin with a 300-kΩ (typical) internal pulldown at power-up; can sense its input voltage, and TI recommends setting GPIOx_INPUT_EN to 0 if unused.
18	GPIO_1	bidirectional	General-purpose input/output pin with a 300-kΩ (typical) internal pulldown at power-up; TI recommends setting GPIOx_INPUT_EN to 0 if unused.
19	CLK_OUT/IDX	bidirectional	Strap input that sets the I2C pullup voltage and device address (via a voltage divider to VDD and GND), and becomes CLK_OUT after start-up; minimum resistance on the pin is 35 kΩ if CLK_OUT is used, or it may be tied to GND if unused.
20	CLKIN	input	Reference clock input; connect to a local clock source in non-sync external clock mode, and it may be left open in other clocking modes.
21	MODE	input	Mode select strap input sampled when PDB transitions LOW to HIGH, typically set with a voltage divider to VDD18 and GND.
22	RES1	input	Reserved pin that must not be connected (leave floating).
23	I2C_SDA	bidirectional	Open-drain I2C data pin, typically pulled up by 470-Ω to 4.7-kΩ resistors to either 1.8-V or 3.3-V depending on the IDX setting; open-drain voltage limit is 3.96 V (absolute maximum).
24	I2C_SCL	bidirectional	Open-drain I2C clock pin, typically pulled up by 470-Ω to 4.7-kΩ resistors to either 1.8-V or 3.3-V depending on the IDX setting; open-drain voltage limit is 3.96 V (absolute maximum).
25	VDDD	power_in	1.8-V (±5%) digital power supply pin, typically decoupled with 1-µF and 0.01-µF capacitors to GND.
26	VDDD_CAP	power_out	Connection for an internal analog regulator decoupling capacitor, typically 10-µF, 0.1-µF and 0.01-µF to GND; do not connect to an external supply rail.
27	GPIO_2	bidirectional	General-purpose input/output pin with a 300-kΩ (typical) internal pulldown at power-up; TI recommends setting GPIOx_INPUT_EN to 0 if unused.
28	GPIO_3	bidirectional	General-purpose input/output pin with a 300-kΩ (typical) internal pulldown at power-up; TI recommends setting GPIOx_INPUT_EN to 0 if unused.
29	CSI_D3P	input	DPHY CSI-2 data input pin; connect to a CSI-2 data source with matched 100-Ω (±5%) impedance interconnects, and it may be left floating if unused.
30	CSI_D3N	input	DPHY CSI-2 data input pin; connect to a CSI-2 data source with matched 100-Ω (±5%) impedance interconnects, and it may be left floating if unused.
31	CSI_D2P	input	DPHY CSI-2 data input pin; connect to a CSI-2 data source with matched 100-Ω (±5%) impedance interconnects, and it may be left floating if unused.
32	CSI_D2N	input	DPHY CSI-2 data input pin; connect to a CSI-2 data source with matched 100-Ω (±5%) impedance interconnects, and it may be left floating if unused.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-32(5x5)
Category	Interface ICs
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage, VDD (VDDD, VDDDRV, VDDPLL)	VDD	-0.3		2.16	V		6
Input voltage (GPIO[3:0], PDB, CLKIN, IDX, MODE, CSI_CLKP/N, CSI_D0P/N to CSI_D3P/N)		-0.3			V		6
V3Link output voltage (DOUT+, DOUT-)		-0.3		1.21	V		6
Open-drain voltage (I2C_SDA, I2C_SCL)		-0.3		3.96	V		6
Junction temperature	TJ			150	°C		6
Storage temperature	Tstg	-65		150	°C		6
Supply voltage VDD (VDDD, VDDDRV, VDDPLL)	VDD	1.71	1.8	1.89	V		7
Open-drain voltage	V(I2C)	1.71		3.6	V	I2C_SDA, I2C_SCL = V(I2C)	7
Operating free-air temperature	TA	-20	25	85	°C		7
MIPI data rate (per CSI-2 lane)		80		832	Mbps		7
Reference clock input frequency		25		104	MHz		7
Local I2C frequency	fI2C			1	MHz		7
Supply noise VDD (VDDD, VDDDRV, VDDPLL)				25	mVp-p		7
Differential supply noise between DOUT+ and DOUT- (PSR)	PSR			25	mVp-p	f = 10 KHz - 50 MHz (coax mode only)	7
Input clock jitter for non-synchronous mode	tJIT			0.05	UI_CLK_IN	Non-synchronous mode	7
Back channel input jitter	tJIT-BC			0.4	UI_BC	DOUT+, DOUT-	7
Supply current (IDD_TOTAL)	IDD_TOTAL		180	225	mA	416-MHz CSI Input Clock, 4 Lane Mode, Checkerboard Pattern	8
Supply current, VDDPLL	IDDPLL		55	80	mA	416-MHz CSI Input Clock, 4 Lane Mode, Checkerboard Pattern	8
Supply current, VDDD	IDDD		45	70	mA	416-MHz CSI Input Clock, 4 Lane Mode, Checkerboard Pattern	8
Supply current, VDDDRV	IDDDRV		60	75	mA	416-MHz CSI Input Clock, 4 Lane Mode, Checkerboard Pattern	8
Low level output voltage (GPIO[3:0], CLK_OUT)	VOL			0.45	V	IOL = +4 mA	8
Input high current (GPIO[3:0], PDB, CLKIN)	IIH			20	µA	VIN = V(VDD)	8
Input low current (GPIO[3:0], PDB, CLKIN)	IIL	-20			µA	VIN = GND	8
Output short-circuit current (LVCMOS)	IOS	-36			mA	VOUT = 0 V	8
Single-ended input voltage	VIN-BC			120	mV	Coaxial configuration, 50 Ω, maximum cable length	8
Differential input voltage	VID-BC			240	mV	STP configuration, 100 Ω, maximum cable length	8
Forward channel eye height	EH-FC	425			mVp-p	Coaxial configuration, V3Link forward channel = 4.16 Gbps	8
Forward channel eye height	EH-FC	850			mVp-p	STP configuration, V3Link forward channel = 4.16 Gbps	8
Forward channel output transition time	tTR-FC			65	ps	V3Link forward channel = 4.16Gbps; 20% to 80%	8
Forward channel output jitter (synchronous mode)	tJIT-FC			0.21	UI	Synchronous mode, measured with f/15 -3dB CDR Loop BW	8
Forward channel output jitter (non-synchronous mode)	tJIT-FC			0.22	UI	Non-synchronous mode, measured with f/15 -3dB CDR Loop BW	8
Internal reference frequency	fREF	24.2		25.5	MHz	Non-synchronous internal clocking mode	8
Output differential voltage	VODp-p	1040	1150	1340	mVp-p	RL = 100 Ω	8
Output voltage imbalance	ΔVOD		5	24	mV		8
Output differential offset voltage	VOS			575	mV		9
Output short-circuit current (differential)	IOS	-22			mA	DOUT = 0 V	9
Internal termination resistance	RT	80	100	120	Ω	Between DOUT+ and DOUT-	9
Output single-ended voltage	VOUT	520	575	670	mVp-p	RL = 50 Ω	9
Output short-circuit current (single-ended)	IOS	-22			mA	DOUT = 0 V	9
Single-ended termination resistance	RT	40	50	60	Ω		9
Voltage accuracy	VACC	-1		1	LSB	See Voltage and Temperature Sensing	9
Temperature accuracy	TACC	-1		1	LSB	See Voltage and Temperature Sensing	9
Common-mode voltage HS receive mode	VCMRX(DC)	70		330	mV	HS receive mode	9
Differential input high threshold	VIDTH			70	mV		9
Differential input low threshold	VIDTL	-70			mV		9
Differential input impedance	ZID	80	100	125	Ω		9
Data to clock setup time (tHOLD as printed)	tHOLD	0.15			UI		9
Data to clock hold time (tSETUP as printed)	tSETUP	0.15			UI		9
Logic high input voltage (CSI-2 LP)	VIH	880			mV		10
Logic low input voltage (CSI-2 LP)	VIL			550	mV		10
Input hysteresis (CSI-2 LP)	VHYST	25		75	mV		10
LVCMOS low-to-high transition time	tCLH			2	ns	V(VDD) = 1.71 to 1.89 V	10
LVCMOS high-to-low transition time	tCHL			2	ns	V(VDD) = 1.71 to 1.89 V	10
PDB reset pulse width	tPDB	3			ms	Voltage supplies applied and stable	10
Input hysteresis (serial control bus)	VHY	50			mV	I2C_SCL, I2C_SDA >50 mV	10
Output low level (serial control bus)	VOL			0.4	V	V(I2C) > 2 V, IOL = 3 mA, Standard-mode/Fast-mode	10
Thermal resistance, junction-to-ambient	RθJA		31.5		°C/W	RHB (VQFN) 32 pins	7
Thermal resistance, junction-to-board	RθJB		10.9		°C/W	RHB (VQFN) 32 pins	7
Thermal resistance, junction-to-case (top)	RθJC(top)		20		°C/W	RHB (VQFN) 32 pins	7
Thermal resistance, junction-to-case (bottom)	RθJC(bot)		1		°C/W	RHB (VQFN) 32 pins	7

CAD (KiCad official)

Symbol: TSER953RHBT
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
3D model files: tser953rhbt-etched.step / tser953rhbt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tser953rhbt.step / tser953rhbt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (86 pp, sha256 a9b8758dc014b9f6, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

TSER953RHBT

Verified TSER953RHBT

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3D Model

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Datasheet

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