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TSC103IDT

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STMicroelectronics Current Sense Amplifiers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentamplifiers-comparatorstsc103idtfactory-2.0.0extractor-text

Verified TSC103IDT

by Ray · last 6 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TSC103IDT · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 25-page datasheet
  • ✓distributor: lcsc C2971373, digikey 497-TSC103IDTTR-ND, mouser 511-TSC103IDT
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-ks2ltl72/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tsc103idt.kicad_sym✓ tsc103idt.kicad_mod✓ tsc103idt.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2h ago
viewers tsc103idt: viewers · Ray 2h ago
package.json Publish 0.1.0 · Ray 2h ago
page.json Set visibility: public · Ray 2h ago
README.md Publish 0.1.0 · Ray 2h ago
tsc103idt-etched.glb Publish 0.1.0 · Ray 2h ago
tsc103idt-etched.step tsc103idt: factory component page (tier=mfr) · Ray 2h ago
tsc103idt-hero.glb tsc103idt: hero GLB from the etched model (keeps the MPN mark) · Ray 2h ago
tsc103idt-hero.overlay.json Publish 0.1.0 · Ray 2h ago
tsc103idt.glb Publish 0.1.0 · Ray 2h ago
tsc103idt.kicad_mod Publish 0.1.0 · Ray 2h ago
tsc103idt.kicad_sym Publish 0.1.0 · Ray 2h ago
tsc103idt.lbr Publish 0.1.0 · Ray 2h ago
tsc103idt.step Publish 0.1.0 · Ray 2h ago
verification.json Verified: Published by the parts factory: tier mfr, 8 pins · Ray 2h ago

TSC103IDT

STMicroelectronics · Current Sense Amplifiers · SOIC-8

TSC103IDT from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Vm input Connection for the external sense resistor, where the measured current exits the shunt on the Vm side; common-mode range 2.9 V to 70 V in single-supply configuration.
2 SEL1 input Gain-select pin; logic low threshold is 0.5 V maximum and logic high threshold is 1.2 VCC minimum.
3 SEL2 input Gain-select pin; logic low threshold is 0.5 V maximum and logic high threshold is 1.2 VCC minimum.
4 Out output The Out voltage is proportional to the magnitude of the sense voltage Vp-Vm, with an absolute maximum range of -0.3 V to Vcc+ + 0.3 V.
5 Vcc+ power_in Positive power supply line; 2.7 V to 5.5 V in single-supply configuration.
6 Gnd power_in Ground line, the reference for single-supply operation with Vcc- connected to it at 0 V.
7 Vcc- power_in Negative power supply line; used in dual-supply configuration from -8 V to 0 V (Vcc+ = 5.5 V max) and maximum Vcc+ to Vcc- difference of 15 V.
8 Vp input Connection for the external sense resistor, where the measured current enters the shunt on the Vp side; Vp and Vm input voltages are limited to -16 V to 75 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SOIC-8
Category Amplifiers/Comparators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Total supply current ICC 200 360 µA Vsense = 0 V, Tmin < Tamb < Tmax 7
Total supply current ICC1 300 480 µA Vsense = 50 mV Av = 50 V/V Tmin < Tamb < Tmax 7
DC common-mode rejection DC CMR 90 105 dB 2.9 V< Vm < 70 V Tmin < Tamb < Tmax 7
AC common-mode rejection AC CMR 95 dB Av = 50 V/V or 100 V/V 2.9 V< Vm < 30 V 1 kHz sine wave 7
Supply voltage rejection SVR 85 95 dB SEL1 = Gnd, SEL2 = Gnd 2.7 V< VCC < 5.5 V Vsense = 30 mV Tmin < Tamb < Tmax 7
Input offset voltage Vos -500 500 µV Tamb = 25 °C 7
Input offset voltage Vos -1100 1100 µV Tmin < Tamb < Tmax 7
Input offset drift vs. T dVos/dT -20 5 µV/°C Av = 50 V/V Tmin < Tamb < Tmax 7
Input leakage current Ilk 1 µA VCC = 0 V Tmin < Tamb < Tmax 7
Input bias current Iib 10 15 µA Vsense = 0 V Tmin < Tamb < Tmax 7
Logic low voltage threshold (SEL1 and SEL2) VIL -0.3 0.5 V VCCmin < VCC < VCCmax Tmin < Tamb < Tmax 7
Logic high voltage threshold (SEL1 and SEL2) VIH 1.2 V VCCmin < VCC < VCCmax Tmin < Tamb < Tmax 7
Gain-select pins (SEL1 and SEL2) input bias current Isel 400 nA SEL pin connected to GND or VCC Tmin < Tamb < Tmax 7
Output voltage drift vs. T ΔVout/ΔT -240 240 ppm/°C Av = 50 V/V Tmin < Tamb < Tmax 8
Output stage load regulation ΔVout/ΔIout -1.5 0.3 1.5 mV/mA -10 mA < Iout <10 mA Iout sink or source current Av = 50 V/V 8
Total output voltage accuracy ΔVout -2.5 2.5 % Vsense = 50 mV Tamb = 25 °C 8
Total output voltage accuracy ΔVout -4 4 % Vsense = 50 mV Tmin < Tamb < Tmax 8
Total output voltage accuracy ΔVout -3.5 3.5 % Vsense = 90 mV Tamb = 25 °C 8
Total output voltage accuracy ΔVout -5 5 % Vsense = 90 mV Tmin < Tamb < Tmax 8
Total output voltage accuracy ΔVout -5.5 5.5 % Vsense = 10 mV Tamb = 25 °C 8
Total output voltage accuracy ΔVout -8 8 % Vsense = 10 mV Tmin < Tamb < Tmax 8
Total output voltage accuracy ΔVout -10 10 % Vsense = 5 mV Tamb = 25 °C 8
Total output voltage accuracy ΔVout -22 22 % Vsense = 5 mV Tmin < Tamb < Tmax 8
Short-circuit current Isc 15 26 mA OUT connected to VCC or GND 8
Output stage high-state saturation voltage VOH 85 135 mV VOH = VCC-Vout Vsense = 1 V Iout = 1 mA 8
Output stage low-state saturation voltage VOL 80 125 mV Vsense =-1 V Iout = 1 mA 8
Response to input differential voltage change (settling to 1%) ts 3 µs Av = 20 V/V Cload = 47 pF Vsense square pulse 500 mV to 3 V 9
Response to input differential voltage change (settling to 1%) ts 4 µs Av = 25 V/V Cload = 47 pF Vsense square pulse 500 mV to 3 V 9
Response to input differential voltage change (settling to 1%) ts 6 µs Av = 50 V/V Cload = 47 pF Vsense square pulse 500 mV to 3 V 9
Response to input differential voltage change (settling to 1%) ts 10 µs Av = 100 V/V Cload = 47 pF Vsense square pulse 500 mV to 3 V 9
Slew rate SR 0.4 0.6 V/µs Vsense = 10 mV to 100 mV 9
Response to a gain change (settling to 1%) tSEL 1 µs Any change of state of SEL1 or SEL2 pin 9
Response to common-mode voltage change (settling to 1%) trec 20 µs Vcc+= 5 V, Vcc-= -5 V Vm step change from -2 V to 30 V or 30 V to -2 V 9
Gain Av 20 V/V SEL1 = Gnd, SEL2 = Gnd 8
Gain Av 25 V/V SEL1 = Gnd, SEL2 = Vcc+ 8
Gain Av 50 V/V SEL1 = Vcc+, SEL2 = Gnd 8
Gain Av 100 V/V SEL1 = Vcc+, SEL2 = Vcc+ 8
3 dB bandwidth BW 700 kHz Cload = 47 pF Vm = 12 V Vsense = 50 mV Av = 50 V/V 9
Equivalent input noise voltage eN 40 nV/√Hz f = 1 kHz 9
Input pins differential voltage (Vp-Vm) Vid -20 20 V 6
Sensing pins input voltages (Vp, Vm) Vin_sense -16 75 V Measured with respect to the Vcc- pin 6
Gain selection pins input voltages (SEL1, SEL2) Vin_sel -0.3 V Measured with respect to Gnd; upper limit Vcc+ +0.3 V 6
Positive supply voltage Vcc+ -0.3 7 V Measured with respect to Gnd 6
DC supply voltage Vcc+-Vcc- 0 15 V 6
DC output pin voltage Vout -0.3 V Measured with respect to Gnd; upper limit Vcc+ +0.3 V 6
Storage temperature Tstg -55 150 °C 6
Maximum junction temperature Tj 150 °C 6
ESD human body model HBM 2.5 kV Human body model, 100 pF through 1.5 kΩ 6
ESD machine model MM 150 V Machine model, 200 pF, internal resistor < 5 Ω 6
ESD charged device model CDM 1.5 kV Charged device model 6
Supply voltage in single-supply configuration Vcc+ 2.7 5.5 V Vcc- connected to Gnd = 0 V, from Tmin to Tmax 6
Negative supply voltage in dual-supply configuration Vcc- -8 0 V Vcc+ = 5.5 V max, from Tmin to Tmax 6
Negative supply voltage in dual-supply configuration Vcc- -11 0 V Vcc+ = 3 V max, from Tmin to Tmax 6
Common-mode voltage range referred to pin Vcc- Vicm 2.9 70 V Tmin to Tmax 6
Operational temperature range Toper -40 125 °C Tmin to Tmax 6
SO8 thermal resistance junction to ambient Rthja 125 °C/W SO8 package 6

CAD (KiCad official)

  • Symbol: TSC103IDT
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tsc103idt-etched.step / tsc103idt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tsc103idt.step / tsc103idt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (25 pp, sha256 d91a799fe933a9b0, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF