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TSB711ILT

Public Made by Adom

by adom

STMicroelectronics Operational Amplifier, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Datasheet

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Contents

README

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TSB711ILT

STMicroelectronics · Operational Amplifier · SOT-23-5

TSB711ILT from STMicroelectronics, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT output Rail-to-rail amplifier output channel.
2 VCC- power_in Negative supply voltage; the total supply range is 2.7 V to 36 V, and the absolute maximum is +40 V or ±20 V.
3 IN+ input Non-inverting input channel; common mode range is (VCC-) to (VCC+) + 0.1 V, and input current must be limited to ±10 mA.
4 IN- input Inverting input channel; input voltage absolute maximum is (VCC-) - 0.2 V to (VCC+) + 0.2 V, and input current must be limited to ±10 mA.
5 VCC+ power_in Positive supply voltage; the total supply range is 2.7 V to 36 V, and the absolute maximum is +40 V or ±20 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SOT-23-5
Category Operational Amplifier/Comparator
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 40 V +40 or ±20 V, referred to network ground 4
Input voltage differential Vid -2 2 V 4
Input current Iin -10 10 mA 4
Storage temperature -65 150 °C 4
Maximum junction temperature Tj 150 °C 4
ESD HBM 2 kV Human body model 4
ESD CDM 1 kV Charged device model 4
Latch-up immunity 100 mA 4
Supply voltage VCC 2.7 36 V 4
Operating free air temperature range Toper -40 125 °C 4
Input offset voltage Vio -800 800 µV VCC=36 V, T = 25 °C, VCC- ≤ VICM ≤ VCC+ - 1.5 V 5
Input offset voltage Vio -1200 1200 µV VCC=36 V, T = 25 °C, VCC- ≤ VICM ≤ VCC+ 5
Input offset voltage Vio -1100 1100 µV VCC=36 V, -40 °C < T < 125 °C, VCC- ≤ VICM ≤ VCC+ - 1.5 V 5
Input offset voltage Vio -1400 1400 µV VCC=36 V, -40 °C < T < 125 °C, VCC- ≤ VICM ≤ VCC+ 5
Input offset voltage Vio -800 800 µV VCC=5 V, T = 25 °C, VCC- ≤ VICM ≤ VCC+ - 1.5 V 8
Input offset voltage Vio -1200 1200 µV VCC=5 V, T = 25 °C, VCC- ≤ VICM ≤ VCC+ 8
Input offset voltage Vio -1100 1100 µV VCC=5 V, -40 °C < T < 125 °C, VCC- ≤ VICM ≤ VCC+ - 1.5 V 8
Input offset voltage Vio -1400 1400 µV VCC=5 V, -40 °C < T < 125 °C, VCC- ≤ VICM ≤ VCC+ 8
Input bias current IIB 0 300 nA VCC=36 V, VICM = VCC+, T = 25 °C 5
Input bias current IIB 0 900 nA VCC=36 V, VICM = VCC+, -40 °C < T < 125 °C 5
Input bias current IIB -100 0 nA VCC=36 V, VICM = VCC-, T = 25 °C 5
Input bias current IIB -200 0 nA VCC=36 V, VICM = VCC-, -40 °C < T < 125 °C 5
Input bias current IIB 0 300 nA VCC=5 V, VICM = VCC+, T = 25 °C 8
Input bias current IIB 0 900 nA VCC=5 V, VICM = VCC+, -40 °C < T < 125 °C 8
Input bias current IIB -100 0 nA VCC=5 V, VICM = VCC-, T = 25 °C 8
Input bias current IIB -200 0 nA VCC=5 V, VICM = VCC-, -40 °C < T < 125 °C 8
Input offset current IIO 10 nA VCC=36 V, VICM = VCC+ 5
Open loop gain AVD 110 125 dB VCC=36 V, RL ≥ 10 kΩ, (VCC-) + 0.5 V ≤ VOUT ≤ (VCC+) - 0.5 V, T = 25 °C 5
Open loop gain AVD 105 dB VCC=36 V, RL ≥ 10 kΩ, (VCC-) + 0.5 V ≤ VOUT ≤ (VCC+) - 0.5 V, -40 °C < T < 125 °C 5
Open loop gain AVD 105 120 dB VCC=5 V, RL ≥ 10 kΩ, (VCC-) + 0.5 V ≤ VOUT ≤ (VCC+) - 0.5 V, T = 25 °C 8
Open loop gain AVD 100 dB VCC=5 V, RL ≥ 10 kΩ, (VCC-) + 0.5 V ≤ VOUT ≤ (VCC+) - 0.5 V, -40 °C < T < 125 °C 8
Common-mode rejection ratio CMR 115 130 dB VCC=36 V, (VCC-) ≤ VICM ≤ (VCC+) - 1.5 V, T = 25 °C 5
Common-mode rejection ratio CMR 110 dB VCC=36 V, (VCC-) ≤ VICM ≤ (VCC+) - 1.5 V, -40 °C < T < 125 °C 5
Common-mode rejection ratio CMR 95 125 dB VCC=5 V, (VCC-) ≤ VICM ≤ (VCC+) - 1.5 V, T = 25 °C 8
Common-mode rejection ratio CMR 90 dB VCC=5 V, (VCC-) ≤ VICM ≤ (VCC+) - 1.5 V, -40 °C < T < 125 °C 8
Power supply rejection ratio SVR 100 125 dB 5 V < (VCC+) - (VCC-) < 36 V, VICM = VCC / 2, -40 °C < T < 125 °C 6
High level output voltage (drop from VCC+) VOH 120 mV VCC=36 V, no load, -40 °C < T < 125 °C 6
High level output voltage (drop from VCC+) VOH 200 mV VCC=36 V, ISOURCE = 2 mA, -40 °C < T < 125 °C 6
High level output voltage (drop from VCC+) VOH 1000 mV VCC=36 V, ISOURCE = 15 mA, -40 °C < T < 125 °C 6
Low level output voltage VOL 120 mV VCC=36 V, no load, -40 °C < T < 125 °C 6
Low level output voltage VOL 200 mV VCC=36 V, ISINK = 2 mA, -40 °C < T < 125 °C 6
Low level output voltage VOL 1000 mV VCC=36 V, ISINK = 15 mA, -40 °C < T < 125 °C 6
Output current ISINK IOUT 25 50 mA VCC=36 V, VOUT = VCC, T = 25 °C 6
Output current ISINK IOUT 20 mA VCC=36 V, VOUT = VCC, -40 °C < T < 125 °C 6
Output current ISOURCE IOUT 25 50 mA VCC=36 V, VOUT = 0 V, T = 25 °C 6
Output current ISOURCE IOUT 20 mA VCC=36 V, VOUT = 0 V, -40 °C < T < 125 °C 6
Supply current by op-amp ICC 1.8 mA VCC=36 V, no load, T = 25 °C 6
Supply current by op-amp ICC 3 mA VCC=36 V, no load, -40 °C < T < 125 °C 6
Supply current by op-amp ICC 1.4 mA VCC=5 V, no load, T = 25 °C 9
Supply current by op-amp ICC 2.3 mA VCC=5 V, no load, -40 °C < T < 125 °C 9
Gain bandwidth product GBP 4.5 6 MHz VCC=36 V, RL = 10 kΩ, CL = 100 pF 6
Slew rate SR 2.2 3 V / µs VCC=36 V, 9 V step, RL = 10 kΩ, CL = 100 pF, AV = 1 V/V, 10% to 90% 6
Gain bandwidth product GBP 4.5 6 MHz VCC=5 V, RL = 10 kΩ, CL = 100 pF 9
Slew rate SR 2 2.7 V / µs VCC=5 V, 3 V step, RL = 10 kΩ, CL = 100 pF, AV = 1 V/V, 10% to 90% 9
Input offset voltage drift ΔVio/ΔT 2.8 µV / °C -40 °C < T < 125 °C 5
Long term input offset voltage drift ΔVio 0.57 µV / √mo T = 25 °C 5
Phase margin Φm 45 ° VCC=36 V, at unity gain, 25 °C, 10 kΩ, 100 pF 6
Input voltage noise density en 20 nV/√Hz VCC=36 V, f = 10 Hz 6
Input current noise density in 0.15 pA/√Hz VCC=36 V, f = 1 kHz 7

CAD (KiCad official)

  • Symbol: TSB711ILT
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tsb711ilt-etched.step / tsb711ilt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tsb711ilt.step / tsb711ilt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (36 pp, sha256 e5c8b3d26c78b30a, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF