TS922IDT
Public Made by Adomby adom
STMicroelectronics Operational Amplifier, SO-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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TS922IDT
STMicroelectronics · Operational Amplifier · SO-8
TS922IDT from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT1 | output | Output of op-amp channel 1. Rail-to-rail output capable of sourcing/sinking up to 80 mA (drives 32 Ω loads). |
| 2 | -IN1 | input | Inverting input of op-amp channel 1. Common-mode input range: (Vcc-)-0.2 V to (Vcc+)+0.2 V. |
| 3 | +IN1 | input | Non-inverting input of op-amp channel 1. Common-mode input range: (Vcc-)-0.2 V to (Vcc+)+0.2 V. |
| 4 | VCC- | power_in | Negative supply rail (or ground in single-supply operation). Supply range: 2.7 V to 12 V between VCC+ and VCC-. Absolute max 14 V. |
| 5 | +IN2 | input | Non-inverting input of op-amp channel 2. Common-mode input range: (Vcc-)-0.2 V to (Vcc+)+0.2 V. |
| 6 | -IN2 | input | Inverting input of op-amp channel 2. Common-mode input range: (Vcc-)-0.2 V to (Vcc+)+0.2 V. |
| 7 | OUT2 | output | Output of op-amp channel 2. Rail-to-rail output capable of sourcing/sinking up to 80 mA (drives 32 Ω loads). |
| 8 | VCC+ | power_in | Positive supply rail. Supply range: 2.7 V to 12 V between VCC+ and VCC-. Absolute max 14 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SO-8 |
| Category | Op-amp/Cmp |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
TS922IDTTS922IDTIPT
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input offset voltage (VCC = 3 V, TS922) | Vio | 3 | mV | 6 | |||
| Input offset voltage (VCC = 3 V, TS922, Tmin to Tmax) | Vio | 5 | mV | Tmin ≤ Tamb ≤ Tmax | 6 | ||
| Input offset current (VCC = 3 V) | Iio | 1 | 30 | nA | Vout = VCC/2 | 6 | |
| Input offset current (VCC = 3 V, Tmin to Tmax) | Iio | 30 | nA | Tmin ≤ Tamb ≤ Tmax | 6 | ||
| Input bias current (VCC = 3 V) | Iib | 15 | 100 | nA | Vout = VCC/2 | 6 | |
| Input bias current (VCC = 3 V, Tmin to Tmax) | Iib | 100 | nA | Tmin ≤ Tamb ≤ Tmax | 6 | ||
| High level output voltage (VCC = 3 V) | VOH | 2.9 | V | RL = 10 kΩ | 6 | ||
| High level output voltage (VCC = 3 V, Tmin to Tmax) | VOH | 2.9 | V | Tmin ≤ Tamb ≤ Tmax | 6 | ||
| High level output voltage (VCC = 3 V) | VOH | 2.87 | V | RL = 600 Ω | 6 | ||
| High level output voltage (VCC = 3 V, Tmin to Tmax) | VOH | 2.87 | V | Tmin ≤ Tamb ≤ Tmax | 6 | ||
| High level output voltage (VCC = 3 V) | VOH | 2.63 | V | RL = 32 Ω | 6 | ||
| Low level output voltage (VCC = 3 V) | VOL | 50 | mV | RL = 10 kΩ | 6 | ||
| Low level output voltage (VCC = 3 V, Tmin to Tmax) | VOL | 50 | mV | Tmin ≤ Tamb ≤ Tmax | 6 | ||
| Low level output voltage (VCC = 3 V) | VOL | 100 | mV | RL = 600 Ω | 6 | ||
| Low level output voltage (VCC = 3 V, Tmin to Tmax) | VOL | 100 | mV | Tmin ≤ Tamb ≤ Tmax | 6 | ||
| Low level output voltage (VCC = 3 V) | VOL | 180 | mV | RL = 32 Ω | 6 | ||
| Large signal voltage gain (VCC = 3 V) | Avd | 200 | V/mV | RL = 10 kΩ, Vout = 2 Vp-p | 6 | ||
| Large signal voltage gain (VCC = 3 V, Tmin to Tmax) | Avd | 70 | V/mV | Tmin ≤ Tamb ≤ Tmax | 6 | ||
| Large signal voltage gain (VCC = 3 V) | Avd | 35 | V/mV | RL = 600 Ω, Vout = 2 Vp-p | 6 | ||
| Large signal voltage gain (VCC = 3 V, Tmin to Tmax) | Avd | 15 | V/mV | Tmin ≤ Tamb ≤ Tmax | 6 | ||
| Large signal voltage gain (VCC = 3 V) | Avd | 16 | V/mV | RL = 32 Ω, Vout = 2 Vp-p | 6 | ||
| Total supply current (VCC = 3 V) | ICC | 2 | 3 | mA | No load, Vout = VCC/2 | 6 | |
| Total supply current (VCC = 3 V, Tmin to Tmax) | ICC | 3.2 | mA | Tmin ≤ Tamb ≤ Tmax | 6 | ||
| Common mode rejection ratio (VCC = 3 V) | CMR | 60 | 80 | dB | Vicm = 0 to 3 V | 6 | |
| Common mode rejection ratio (VCC = 3 V, Tmin to Tmax) | CMR | 56 | dB | Tmin ≤ Tamb ≤ Tmax | 6 | ||
| Supply voltage rejection ratio (VCC = 3 V) | SVR | 60 | 85 | dB | VCC = 2.7 to 3.3 V | 6 | |
| Supply voltage rejection ratio (VCC = 3 V, Tmin to Tmax) | SVR | 60 | dB | Tmin ≤ Tamb ≤ Tmax | 6 | ||
| Output short-circuit current (VCC = 3 V) | Io | 50 | 80 | mA | 6 | ||
| Slew rate (VCC = 3 V) | SR | 0.7 | 1.3 | V/μs | 6 | ||
| Absolute maximum supply voltage | VCC | 14 | V | 4 | |||
| Differential input voltage | Vid | -1 | 1 | V | Non-inverting input relative to inverting input; if /Vid/ > 1 V, input current must not exceed 1 mA | 4 | |
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Maximum junction temperature | Tj | 150 | °C | 4 | |||
| Soldering temperature (10 s), leaded version | 250 | °C | 10 s, leaded version | 4 | |||
| Soldering temperature (10 s), unleaded version | 260 | °C | 10 s, unleaded version | 4 | |||
| ESD HBM (human body model) | 2000 | V | Human body model | 4 | |||
| ESD MM (machine model) | 120 | V | Machine model | 4 | |||
| ESD CDM (charged device model) | 1500 | V | Charged device model | 4 | |||
| Latch-up immunity | 200 | mA | 4 | ||||
| Supply voltage (operating) | VCC | 2.7 | 12 | V | 5 | ||
| Operating free air temperature range | Toper | -40 | 125 | °C | 5 | ||
| Input offset voltage drift | ΔVio/ΔT | 2 | μV/°C | 6 | |||
| Gain bandwidth product (VCC = 3 V) | GBP | 4 | MHz | RL = 600 Ω | 6 | ||
| Phase margin at unit gain (VCC = 3 V) | ɸm | 68 | Degrees | RL = 600 Ω, CL = 100 pF | 6 | ||
| Gain margin (VCC = 3 V) | Gm | 12 | dB | RL = 600 Ω, CL = 100 pF | 7 | ||
| Equivalent input noise voltage | en | 9 | nV/√Hz | f = 1 kHz | 7 | ||
| Total harmonic distortion | THD | 0.005 | % | Vout = 2 Vp-p, f = 1 kHz, Av = 1, RL = 600 Ω | 7 | ||
| Channel separation | Cs | 120 | dB | 7 | |||
| Thermal resistance junction-to-ambient, SO8 | Rthja | 125 | °C/W | SO8 package; values are typical (AMR note 4) | 4 | ||
| Thermal resistance junction-to-case, SO8 | Rthjc | 40 | °C/W | SO8 package; values are typical (AMR note 4) | 4 |
CAD (KiCad official)
- Symbol:
TS922IDT - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
ts922idt-etched.step/ts922idt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ts922idt.step/ts922idt.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
ts922idt.step |
122 KB | You want the bare part, or you mark your own boards. |
ts922idt-etched.step |
1.7 MB | You want the part with TS922IDT already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 431 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (22 pp, sha256
9b86a016a7b3d7e4, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TS922IDT
**STMicroelectronics** · Operational Amplifier · SO-8
TS922IDT from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT1 | output | Output of op-amp channel 1. Rail-to-rail output capable of sourcing/sinking up to 80 mA (drives 32 Ω loads). |
| 2 | -IN1 | input | Inverting input of op-amp channel 1. Common-mode input range: (Vcc-)-0.2 V to (Vcc+)+0.2 V. |
| 3 | +IN1 | input | Non-inverting input of op-amp channel 1. Common-mode input range: (Vcc-)-0.2 V to (Vcc+)+0.2 V. |
| 4 | VCC- | power_in | Negative supply rail (or ground in single-supply operation). Supply range: 2.7 V to 12 V between VCC+ and VCC-. Absolute max 14 V. |
| 5 | +IN2 | input | Non-inverting input of op-amp channel 2. Common-mode input range: (Vcc-)-0.2 V to (Vcc+)+0.2 V. |
| 6 | -IN2 | input | Inverting input of op-amp channel 2. Common-mode input range: (Vcc-)-0.2 V to (Vcc+)+0.2 V. |
| 7 | OUT2 | output | Output of op-amp channel 2. Rail-to-rail output capable of sourcing/sinking up to 80 mA (drives 32 Ω loads). |
| 8 | VCC+ | power_in | Positive supply rail. Supply range: 2.7 V to 12 V between VCC+ and VCC-. Absolute max 14 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SO-8 |
| Category | Op-amp/Cmp |
| Pins | 8 |
## Ordering variants
Same part, different packaging or reel option.
- `TS922IDT`
- `TS922IDTIPT`
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input offset voltage (VCC = 3 V, TS922) | Vio | | | 3 | mV | | 6 |
| Input offset voltage (VCC = 3 V, TS922, Tmin to Tmax) | Vio | | | 5 | mV | Tmin ≤ Tamb ≤ Tmax | 6 |
| Input offset current (VCC = 3 V) | Iio | | 1 | 30 | nA | Vout = VCC/2 | 6 |
| Input offset current (VCC = 3 V, Tmin to Tmax) | Iio | | | 30 | nA | Tmin ≤ Tamb ≤ Tmax | 6 |
| Input bias current (VCC = 3 V) | Iib | | 15 | 100 | nA | Vout = VCC/2 | 6 |
| Input bias current (VCC = 3 V, Tmin to Tmax) | Iib | | | 100 | nA | Tmin ≤ Tamb ≤ Tmax | 6 |
| High level output voltage (VCC = 3 V) | VOH | 2.9 | | | V | RL = 10 kΩ | 6 |
| High level output voltage (VCC = 3 V, Tmin to Tmax) | VOH | 2.9 | | | V | Tmin ≤ Tamb ≤ Tmax | 6 |
| High level output voltage (VCC = 3 V) | VOH | 2.87 | | | V | RL = 600 Ω | 6 |
| High level output voltage (VCC = 3 V, Tmin to Tmax) | VOH | 2.87 | | | V | Tmin ≤ Tamb ≤ Tmax | 6 |
| High level output voltage (VCC = 3 V) | VOH | 2.63 | | | V | RL = 32 Ω | 6 |
| Low level output voltage (VCC = 3 V) | VOL | | | 50 | mV | RL = 10 kΩ | 6 |
| Low level output voltage (VCC = 3 V, Tmin to Tmax) | VOL | | | 50 | mV | Tmin ≤ Tamb ≤ Tmax | 6 |
| Low level output voltage (VCC = 3 V) | VOL | | | 100 | mV | RL = 600 Ω | 6 |
| Low level output voltage (VCC = 3 V, Tmin to Tmax) | VOL | | | 100 | mV | Tmin ≤ Tamb ≤ Tmax | 6 |
| Low level output voltage (VCC = 3 V) | VOL | | | 180 | mV | RL = 32 Ω | 6 |
| Large signal voltage gain (VCC = 3 V) | Avd | 200 | | | V/mV | RL = 10 kΩ, Vout = 2 Vp-p | 6 |
| Large signal voltage gain (VCC = 3 V, Tmin to Tmax) | Avd | 70 | | | V/mV | Tmin ≤ Tamb ≤ Tmax | 6 |
| Large signal voltage gain (VCC = 3 V) | Avd | 35 | | | V/mV | RL = 600 Ω, Vout = 2 Vp-p | 6 |
| Large signal voltage gain (VCC = 3 V, Tmin to Tmax) | Avd | 15 | | | V/mV | Tmin ≤ Tamb ≤ Tmax | 6 |
| Large signal voltage gain (VCC = 3 V) | Avd | 16 | | | V/mV | RL = 32 Ω, Vout = 2 Vp-p | 6 |
| Total supply current (VCC = 3 V) | ICC | | 2 | 3 | mA | No load, Vout = VCC/2 | 6 |
| Total supply current (VCC = 3 V, Tmin to Tmax) | ICC | | | 3.2 | mA | Tmin ≤ Tamb ≤ Tmax | 6 |
| Common mode rejection ratio (VCC = 3 V) | CMR | 60 | 80 | | dB | Vicm = 0 to 3 V | 6 |
| Common mode rejection ratio (VCC = 3 V, Tmin to Tmax) | CMR | 56 | | | dB | Tmin ≤ Tamb ≤ Tmax | 6 |
| Supply voltage rejection ratio (VCC = 3 V) | SVR | 60 | 85 | | dB | VCC = 2.7 to 3.3 V | 6 |
| Supply voltage rejection ratio (VCC = 3 V, Tmin to Tmax) | SVR | 60 | | | dB | Tmin ≤ Tamb ≤ Tmax | 6 |
| Output short-circuit current (VCC = 3 V) | Io | 50 | 80 | | mA | | 6 |
| Slew rate (VCC = 3 V) | SR | 0.7 | 1.3 | | V/μs | | 6 |
| Absolute maximum supply voltage | VCC | | | 14 | V | | 4 |
| Differential input voltage | Vid | -1 | | 1 | V | Non-inverting input relative to inverting input; if /Vid/ > 1 V, input current must not exceed 1 mA | 4 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 4 |
| Maximum junction temperature | Tj | | | 150 | °C | | 4 |
| Soldering temperature (10 s), leaded version | | | | 250 | °C | 10 s, leaded version | 4 |
| Soldering temperature (10 s), unleaded version | | | | 260 | °C | 10 s, unleaded version | 4 |
| ESD HBM (human body model) | | | | 2000 | V | Human body model | 4 |
| ESD MM (machine model) | | | | 120 | V | Machine model | 4 |
| ESD CDM (charged device model) | | | | 1500 | V | Charged device model | 4 |
| Latch-up immunity | | | | 200 | mA | | 4 |
| Supply voltage (operating) | VCC | 2.7 | | 12 | V | | 5 |
| Operating free air temperature range | Toper | -40 | | 125 | °C | | 5 |
| Input offset voltage drift | ΔVio/ΔT | | 2 | | μV/°C | | 6 |
| Gain bandwidth product (VCC = 3 V) | GBP | | 4 | | MHz | RL = 600 Ω | 6 |
| Phase margin at unit gain (VCC = 3 V) | ɸm | | 68 | | Degrees | RL = 600 Ω, CL = 100 pF | 6 |
| Gain margin (VCC = 3 V) | Gm | | 12 | | dB | RL = 600 Ω, CL = 100 pF | 7 |
| Equivalent input noise voltage | en | | 9 | | nV/√Hz | f = 1 kHz | 7 |
| Total harmonic distortion | THD | | 0.005 | | % | Vout = 2 Vp-p, f = 1 kHz, Av = 1, RL = 600 Ω | 7 |
| Channel separation | Cs | | 120 | | dB | | 7 |
| Thermal resistance junction-to-ambient, SO8 | Rthja | | 125 | | °C/W | SO8 package; values are typical (AMR note 4) | 4 |
| Thermal resistance junction-to-case, SO8 | Rthjc | | 40 | | °C/W | SO8 package; values are typical (AMR note 4) | 4 |
## CAD (KiCad official)
- Symbol: `TS922IDT`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `ts922idt-etched.step` / `ts922idt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ts922idt.step` / `ts922idt.glb` are the bare package body.
## 3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
| [`ts922idt.step`](ts922idt.step) | 122 KB | You want the bare part, or you mark your own boards. |
| [`ts922idt-etched.step`](ts922idt-etched.step) | 1.7 MB | You want the part with `TS922IDT` already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a
texture or a decal: 431 faces against 147 in the bare model. It
survives export, section views, and rendering in any CAD tool, and it drops straight
into KiCad or Fusion with no extra setup.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STMicroelectronics datasheet](https://www.st.com/resource/en/datasheet/ts922idt.pdf) (22 pp, sha256 `9b86a016a7b3d7e4`, retrieved 2026-08-17, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ts922idt-datasheet.pdf)