component
TS921IDT
Public Made by Adomby adom
STMicroelectronics Operational Amplifier, SO-8. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTS921IDT
STMicroelectronics · Operational Amplifier · SO-8
TS921IDT from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | N.C. | unconnected | No internal connection. |
| 2 | Inverting input | input | Inverting input of the amplifier; differential input voltage must not exceed ±1 V (add a series resistor limiting input current to ±1 mA otherwise). |
| 3 | Non-inverting input | input | Non-inverting input of the amplifier; rail-to-rail common mode range of VDD - 0.2 V to VCC + 0.2 V. |
| 4 | VDD | power_in | Negative supply terminal (ground in single-supply use); with VCC the supply range is 2.7 V to 12 V. |
| 5 | N.C. | unconnected | No internal connection. |
| 6 | Output | output | Rail-to-rail amplifier output with about 80 mA short-circuit current, no internal short-circuit protection, stable for capacitive loads up to 500 pF. |
| 7 | VCC+ | power_in | Positive supply terminal, 2.7 V to 12 V operating and 14 V absolute maximum. |
| 8 | N.C. | unconnected | No internal connection. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SO-8 |
| Category | Amplifiers/Comparators |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input offset voltage (25 °C limit) | Vio | 3 | mV | VCC = 3 V, Tamb = 25 °C | 4 | ||
| Input offset voltage (over temperature) | Vio | 5 | mV | VCC = 3 V, at Tmin. ≤ Tamb ≤ Tmax | 4 | ||
| Input offset voltage drift | ΔVio | 2 | μV/°C | VCC = 3 V | 4 | ||
| Input offset current | Iio | 1 | 30 | nA | VCC = 3 V, Vout = 1.5 V | 4 | |
| Input bias current | Iib | 15 | 100 | nA | VCC = 3 V, Vout = 1.5 V | 4 | |
| High level output voltage | VOH | 2.87 | V | VCC = 3 V, RL = 600 Ω | 4 | ||
| High level output voltage | VOH | 2.63 | V | VCC = 3 V, RL = 32 Ω | 4 | ||
| Low level output voltage | VOL | 180 | mV | VCC = 3 V, RL = 600 Ω | 4 | ||
| Low level output voltage | VOL | 100 | mV | VCC = 3 V, RL = 32 Ω | 4 | ||
| Large signal voltage gain | Avd | 35 | V/mV | VCC = 3 V, Vout = 2 Vpk-pk, RL = 600 Ω | 4 | ||
| Large signal voltage gain | Avd | 16 | V/mV | VCC = 3 V, Vout = 2 Vpk-pk, RL = 32 Ω | 4 | ||
| Gain bandwidth product | GBP | 4 | MHz | VCC = 3 V, RL = 600 Ω | 4 | ||
| Supply current | ICC | 1 | 1.5 | mA | VCC = 3 V, No load, Vout = VCC/2 | 4 | |
| Common mode rejection ratio | CMR | 60 | 80 | dB | VCC = 3 V | 4 | |
| Supply voltage rejection ratio | SVR | 60 | 80 | dB | VCC = 2.7 to 3.3 V | 4 | |
| Output short-circuit current | Io | 50 | 80 | mA | VCC = 3 V | 4 | |
| Slew rate | SR | 0.7 | 1.3 | V/μs | VCC = 3 V | 4 | |
| Phase margin at unit gain | Pm | 68 | Degrees | VCC = 3 V, RL = 600 Ω, CL = 100 pF | 4 | ||
| Gain margin | GM | 12 | dB | VCC = 3 V, RL = 600 Ω, CL = 100 pF | 4 | ||
| Equivalent input noise voltage | en | 9 | nV/√Hz | VCC = 3 V, f = 1 kHz | 4 | ||
| Total harmonic distortion | THD | 0.005 | % | VCC = 3 V, Vout = 2 Vpk-pk, f = 1 kHz, Av = 1, RL = 600 Ω | 4 | ||
| Input offset voltage (25 °C limit) | Vio | 3 | mV | VCC = 5 V, Tamb = 25 °C | 5 | ||
| Input offset voltage (over temperature) | Vio | 5 | mV | VCC = 5 V, at Tmin. ≤ Tamb ≤ Tmax | 5 | ||
| Input offset voltage drift | ΔVio | 2 | μV/°C | VCC = 5 V | 5 | ||
| Input offset current | Iio | 1 | 30 | nA | VCC = 5 V, Vout = 1.5 V | 5 | |
| Input bias current | Iib | 15 | 100 | nA | VCC = 5 V, Vout = 1.5 V | 5 | |
| High level output voltage | VOH | 4.85 | V | VCC = 5 V, RL = 600 Ω | 5 | ||
| High level output voltage | VOH | 4.4 | V | VCC = 5 V, RL = 32 Ω | 5 | ||
| Low level output voltage | VOL | 300 | mV | VCC = 5 V, RL = 600 Ω | 5 | ||
| Low level output voltage | VOL | 120 | mV | VCC = 5 V, RL = 32 Ω | 5 | ||
| Large signal voltage gain | Avd | 35 | V/mV | VCC = 5 V, Vout = 2 Vpk-pk, RL = 600 Ω | 5 | ||
| Large signal voltage gain | Avd | 16 | V/mV | VCC = 5 V, Vout = 2 Vpk-pk, RL = 32 Ω | 5 | ||
| Gain bandwidth product | GBP | 4 | MHz | VCC = 5 V, RL = 600 Ω | 5 | ||
| Supply current | ICC | 1 | 1.5 | mA | VCC = 5 V, No load, Vout = VCC/2 | 5 | |
| Common mode rejection ratio | CMR | 60 | 80 | dB | VCC = 5 V | 5 | |
| Supply voltage rejection ratio | SVR | 60 | 80 | dB | VCC = 4.5 to 5.5 V | 5 | |
| Output short-circuit current | Io | 50 | 80 | mA | VCC = 5 V | 5 | |
| Slew rate | SR | 0.7 | 1.3 | V/μs | VCC = 5 V | 5 | |
| Phase margin at unit gain | Pm | 68 | Degrees | VCC = 5 V, RL = 600 Ω, CL = 100 pF | 5 | ||
| Gain margin | GM | 12 | dB | VCC = 5 V, RL = 600 Ω, CL = 100 pF | 5 | ||
| Equivalent input noise voltage | en | 9 | nV/√Hz | VCC = 5 V, f = 1 kHz | 5 | ||
| Total harmonic distortion | THD | 0.005 | % | VCC = 5 V, Vout = 2 Vpk-pk, f = 1 kHz, Av = 1, RL = 600 Ω | 5 | ||
| Supply voltage | VCC | 14 | V | 3 | |||
| Differential input voltage | Vid | -1 | 1 | V | Differential voltage; if Vid > ±1 V, maximum input current must not exceed ±1 mA | 3 | |
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Maximum junction temperature | Tj | 150 | °C | 3 | |||
| Thermal resistance junction-to-ambient (SO-8) | Rthja | 125 | °C/W | SO-8 package | 3 | ||
| Thermal resistance junction-to-case (SO-8) | Rthjc | 40 | °C/W | SO-8 package | 3 | ||
| ESD human body model | HBM | 1.5 | kV | Human body model (100 pF through 1.5 kΩ) | 3 | ||
| ESD machine model | MM | 100 | V | Machine model (200 pF, internal resistor < 5 Ω) | 3 | ||
| ESD charged device model | CDM | 1.5 | kV | Charged device model | 3 | ||
| Latch-up immunity | 200 | mA | 3 | ||||
| Soldering temperature | 250 | °C | 10 sec., standard package | 3 | |||
| Soldering temperature | 260 | °C | 10 sec., lead-free package | 3 | |||
| Supply voltage | VCC | 2.7 | 12 | V | 3 | ||
| Operating free air temperature range | Toper | -40 | 125 | °C | 3 |
CAD (KiCad official)
- Symbol:
TS921IDT - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
ts921idt-etched.step/ts921idt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ts921idt.step/ts921idt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (16 pp, sha256
14666f98057d4f23, retrieved 2026-10-21, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).