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TS332IDT

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STMicroelectronics Comparators, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TS332IDT

STMicroelectronics · Comparators · SO-8

TS332IDT from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT1 output Open-drain output of comparator 1, which can be pulled up to at most 5.5 V.
2 IN1- input Inverting input of comparator 1, with a rail-to-rail input range of (VCC-) - 0.3 V to (VCC+) + 0.3 V.
3 IN1+ input Non-inverting input of comparator 1, with a rail-to-rail input range of (VCC-) - 0.3 V to (VCC+) + 0.3 V.
4 VCC- power_in Negative supply, or ground, which is the reference for all voltages except differential voltage.
5 IN2+ input Non-inverting input of comparator 2, with a rail-to-rail input range of (VCC-) - 0.3 V to (VCC+) + 0.3 V.
6 IN2- input Inverting input of comparator 2, with a rail-to-rail input range of (VCC-) - 0.3 V to (VCC+) + 0.3 V.
7 OUT2 output Open-drain output of comparator 2, which can be pulled up to at most 5.5 V.
8 VCC+ power_in Positive supply, operating from 1.6 V to 5.0 V (absolute maximum 5.5 V).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SO-8
Category Amplifiers/Comparators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 5.5 V Referenced to VCC- 4
Differential input voltage VID -5.5 5.5 V 4
Input voltage range VIN -0.3 0.3 V (VCC-) - 0.3 to (VCC+) + 0.3 4
Output voltage Vout 5.5 V Referenced to VCC- 4
Storage temperature Tstg -65 150 °C 4
Junction temperature Tj 150 °C 4
Lead temperature TLEAD 260 °C Soldering 10 seconds 4
ESD HBM ESD 2000 V Human body model, JESD22-A114F 4
ESD MM ESD 200 V Machine model, JESD22-A115A 4
ESD CDM ESD 1500 V Charged device model, ANSI/ESD STM5.3.1 4
Latchup immunity 200 mA 4
Thermal resistance junction to ambient Rthja 125 °C/W SO8 4
Thermal resistance junction to case Rthjc 40 °C/W SO8 4
Operating temperature range Toper -40 125 °C 5
Supply voltage VCC 1.6 5 V -40°C < Tamb < +125°C, (VCC+) - (VCC-) 5
Input offset voltage VIO 0.5 5 mV VCC+ = 1.8 V, Tamb = 25°C 6
Input offset voltage over temperature VIO 6 mV VCC+ = 1.8 V, -40 °C < Tamb < +125 °C 6
Input offset voltage drift ΔVio/ΔT 4.5 µV/°C VCC+ = 1.8 V, -40 °C < Tamb < +125 °C 6
Input bias current IIB 25 40 nA VCC+ = 1.8 V, Tamb = 25°C 6
Input offset current IIO 1 10 nA VCC+ = 1.8 V, Tamb = 25°C 6
Supply current, output low ICC 20 26 µA VCC+ = 1.8 V, No load, output low, VICM = 0 V 6
Supply current, output high ICC 22 29 µA VCC+ = 1.8 V, No load, output high, VICM = 0 V 6
Output current leakage IOH 1 10 nA VCC+ = 1.8 V, VOUT = VCC+ 6
Output voltage low VOL 24 30 mV VCC+ = 1.8 V, ISINK = 1 mA 6
Output sink current ISINK 20 22 mA VCC+ = 1.8 V, VOUT = 1.5 V 6
Common mode rejection ratio CMRR 50 68 dB VCC+ = 1.8 V, 0 < VICM < 1.8 V 6
Propagation delay high to low TPHL 210 310 ns VCC+ = 1.8 V, VICM = 0 V, RL = 5.1 kΩ, CL = 50 pF, overdrive = 100 mV 6
Propagation delay low to high TPLH 420 620 ns VCC+ = 1.8 V, VICM = 0 V, RL = 5.1 kΩ, CL = 50 pF, overdrive = 100 mV 6
Input offset voltage VIO 0.5 5 mV VCC+ = 2.7 V, Tamb = 25°C 7
Input offset voltage over temperature VIO 6 mV VCC+ = 2.7 V, -40 °C < Tamb < +125 °C 7
Input offset voltage drift ΔVio/ΔT 3.3 µV/°C VCC+ = 2.7 V, -40 °C < Tamb < +125 °C 7
Input bias current IIB 25 40 nA VCC+ = 2.7 V, Tamb = 25°C 7
Input offset current IIO 1 10 nA VCC+ = 2.7 V, Tamb = 25°C 7
Supply current, output low ICC 21 27 µA VCC+ = 2.7 V, No load, output low, VICM = 0 V 7
Supply current, output high ICC 23 30 µA VCC+ = 2.7 V, No load, output high, VICM = 0 V 7
Output current leakage IOH 1 10 nA VCC+ = 2.7 V, VOUT = VCC+ 7
Output voltage low VOL 17 30 mV VCC+ = 2.7 V, ISINK = 1 mA 7
Output sink current ISINK 40 47 mA VCC+ = 2.7 V, VOUT = 1.5 V 7
Common mode rejection ratio CMRR 54 74 dB VCC+ = 2.7 V, 0 < VICM < 2.7 V 7
Propagation delay high to low TPHL 220 320 ns VCC+ = 2.7 V, VICM = 0 V, RL = 5.1 kΩ, CL = 50 pF, overdrive = 100 mV 7
Propagation delay low to high TPLH 420 640 ns VCC+ = 2.7 V, VICM = 0 V, RL = 5.1 kΩ, CL = 50 pF, overdrive = 100 mV 7
Input offset voltage VIO 0.5 5 mV VCC+ = 5 V, Tamb = 25°C 8
Input offset voltage over temperature VIO 6 mV VCC+ = 5 V, -40 °C < Tamb < +125 °C 8
Input offset voltage drift ΔVio/ΔT 1.3 µV/°C VCC+ = 5 V, -40 °C < Tamb < +125 °C 8
Input bias current IIB 30 40 nA VCC+ = 5 V, Tamb = 25°C 8
Input offset current IIO 1 10 nA VCC+ = 5 V, Tamb = 25°C 8
Supply current, output low ICC 23 30 µA VCC+ = 5 V, No load, output low, VICM = 0 V 8
Supply current, output high ICC 26 34 µA VCC+ = 5 V, No load, output high, VICM = 0 V 8
Output current leakage IOH 1 10 nA VCC+ = 5 V, VOUT = VCC+ 8
Output voltage low VOL 48 60 mV VCC+ = 5 V, ISINK = 1 mA 8
Output sink current ISINK 82 93 mA VCC+ = 5 V, VOUT = 1.5 V 8
Voltage gain AV 40 100 V/mV VCC+ = 5 V 8
Common mode rejection ratio CMRR 60 79 dB VCC+ = 5 V, 0 < VICM < 5 V 8
Supply voltage rejection SVR 56 75 dB VCC+ = 5 V, ΔVCC = 1.8 to 5 V 8
Propagation delay high to low TPHL 270 430 ns VCC+ = 5 V, VICM = 0 V, RL = 5.1 kΩ, CL = 50 pF, overdrive = 100 mV 8
Propagation delay low to high TPLH 450 720 ns VCC+ = 5 V, VICM = 0 V, RL = 5.1 kΩ, CL = 50 pF, overdrive = 100 mV 8

CAD (KiCad official)

  • Symbol: TS332IDT
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: ts332idt-etched.step / ts332idt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ts332idt.step / ts332idt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (27 pp, sha256 f2184bc5c3a980e7, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF